Home
last modified time | relevance | path

Searched refs:v102 (Results 1 – 25 of 32) sorted by relevance

12

/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dreserve-vgpr-for-sgpr-spill.ll34 ,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109}
79 ,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109}
121 ,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109}
170 ,~{v100},~{v101},~{v102},~{v103},~{v104},~{v105},~{v106},~{v107},~{v108},~{v109}
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dswp-epilog-phi7.ll128 %v101 = phi <16 x i32> [ %v12, %b1 ], [ %v102, %b2 ]
129 %v102 = phi <16 x i32> [ %v14, %b1 ], [ %v120, %b2 ]
141 %v114 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v102, <16 x i32> %v101, i32 1)
153 %v126 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v120, <16 x i32> %v102, i32 1)
194 %v159 = phi <16 x i32> [ %v102, %b3 ], [ %v12, %b0 ]
Dswp-phi.ll116 %v102 = getelementptr inbounds [400 x float], [400 x float]* %v0, i32 0, i32 %v101
117 %v103 = load float, float* %v102, align 4, !tbaa !0
Daggr-licm.ll122 %v102 = add nsw i32 %v6, 8
124 %v104 = zext i32 %v102 to i64
Dreg-scavengebug.ll136 %v102 = load <16 x i32>, <16 x i32>* %v84, align 64, !tbaa !0
137 %v103 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v101, <16 x i32> %v102)
143 %v109 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v102, <16 x i32> undef, i32 16)
Dfltnvjump.ll167 %v102 = load i16, i16* %v0, align 2, !tbaa !4
168 call void @f6(i16* %v100, i16 signext %v94, i16* %v101, i16 signext %v102)
Dswp-conv3x3-nested.ll58 %v16 = phi i8* [ %v2, %b1 ], [ %v102, %b5 ]
155 %v102 = getelementptr inbounds i8, i8* %v16, i32 %v13
Dregisterscavenger-fail1.ll198 %v102 = fadd double undef, 1.000000e+00
199 %v103 = fptosi double %v102 to i32
Dlate_instr.ll129 %v102 = tail call <16 x i32> @llvm.hexagon.V6.vmaxub(<16 x i32> %v98, <16 x i32> %v100)
131 %v104 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v95, <16 x i32> %v102)
Dreg-scavengebug-5.ll65 %v47 = phi <16 x i32> [ %v102, %b2 ], [ %v8, %b1 ]
124 %v102 = load <16 x i32>, <16 x i32>* %v84, align 64
144 %v120 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v115, <16 x i32> %v102, i32 1)
DSUnit-boundary-prob.ll138 …%v102 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> %v100, <16 x i32> %v101, i32 16…
139 %v103 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v102, <16 x i32> %v99) #2
Dcext-ice.ll211 %v102 = add nsw i32 %v101, 268435456
212 %v103 = inttoptr i32 %v102 to i32*
Dswp-sigma.ll155 %v102 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v100) #2
156 %v103 = tail call <16 x i32> @llvm.hexagon.V6.vmpyhvsrs(<16 x i32> %v101, <16 x i32> %v102) #2
Dlarge-number-of-preds.ll167 %v102 = getelementptr inbounds [8 x float], [8 x float]* %v1, i32 0, i32 6
168 store float %v94, float* %v102, align 8, !tbaa !0
Dbug14859-split-const-block-addr.ll243 %v102 = load i8, i8* %v101, align 1, !tbaa !4
245 %v104 = call zeroext i1 %a6(i8 zeroext %v102, i8 zeroext %v103)
Dreg-scavengebug-4.ll19 %v2 = phi <16 x i32>* [ undef, %b1 ], [ %v102, %b4 ]
125 %v102 = getelementptr inbounds <16 x i32>, <16 x i32>* %v2, i32 1
Dregscavenger_fail_hwloop.ll127 %v102 = mul i32 %v101, -5
133 %v108 = add i32 %v107, %v102
Dlsr-post-inc-cross-use-offsets.ll165 %v102 = bitcast i8* %v101 to <32 x i32>*
166 %v103 = load <32 x i32>, <32 x i32>* %v102, align 1, !tbaa !4
Dexpand-vstorerw-undef2.ll161 %v102 = tail call <32 x i32> @llvm.hexagon.V6.vsubhsat.128B(<32 x i32> %v100, <32 x i32> %v101) #2
162 %v103 = tail call <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32> undef, <32 x i32> %v102) #2
Dreg-scav-imp-use-dbl-vec.ll195 %v102 = shl nsw i32 %v49, 6
196 %v103 = getelementptr inbounds i16, i16* %v37, i32 %v102
Dregscavengerbug.ll184 %v102 = load double, double* %v44, align 8, !tbaa !6
186 store double %v102, double* %v103, align 8, !tbaa !6
/external/llvm-project/llvm/test/CodeGen/X86/
Dpseudo_cmov_lower.ll140 <8 x double> %v102, <8 x double> %v103,
185 %t103 = fsub <8 x double> %v103, %v102
197 %t101 = select i1 %cmp, <8 x double> %v102, <8 x double> %t103
/external/llvm/test/CodeGen/X86/
Dpseudo_cmov_lower.ll140 <8 x double> %v102, <8 x double> %v103,
185 %t103 = fsub <8 x double> %v103, %v102
197 %t101 = select i1 %cmp, <8 x double> %v102, <8 x double> %t103
/external/llvm-project/llvm/test/Transforms/LoopVectorize/Hexagon/
Dminimum-vf.ll130 %v102 = getelementptr inbounds i8, i8* %v14, i32 %v101
131 %v103 = load i8, i8* %v102, align 1, !tbaa !8
/external/XNNPACK/models/
Dfp32-mobilenet-v3-large.cc122 alignas(16) static std::array<float, 240> v102; in FP32MobileNetV3Large() local
368 std::generate(v102.begin(), v102.end(), std::ref(f32rng)); in FP32MobileNetV3Large()
3590 v101.data() /* input */, v102.data() /* output */, in FP32MobileNetV3Large()
3600 v102.data() /* input */, v103.data() /* output */, in FP32MobileNetV3Large()

12