| /external/llvm/include/llvm/CodeGen/ |
| D | MachineValueType.h | 85 v128i16 = 37, //128 x i16 enumerator
279 return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 || in is2048BitVector()
341 case v128i16: return i16; in getVectorElementType()
379 case v128i16: return 128; in getVectorNumElements()
509 case v128i16: in getSizeInBits()
621 if (NumElements == 128) return MVT::v128i16; in getVectorVT()
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| D | ValueTypes.td | 62 def v128i16: ValueType<2048,37>; //128 x i16 vector value
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonCallingConv.td | 102 CCIfType<[v64i32,v128i16,v256i8],
108 CCIfType<[v64i32,v128i16,v256i8],
128 CCIfType<[v64i32,v128i16,v256i8],
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| D | HexagonRegisterInfo.td | 297 [v64i16, v128i16, v64i16]>;
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| D | HexagonISelLoweringHVX.cpp | 19 static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 };
48 addRegisterClass(MVT::v128i16, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonCallingConv.td | 132 CCIfType<[v64i32,v128i16,v256i8],
138 CCIfType<[v64i32,v128i16,v256i8],
158 CCIfType<[v64i32,v128i16,v256i8],
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| D | HexagonRegisterInfo.td | 333 [v64i16, v128i16, v64i16]>;
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| D | HexagonISelLoweringHVX.cpp | 24 static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 };
52 addRegisterClass(MVT::v128i16, &Hexagon::HvxWRRegClass); in initializeHVXLowering()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/ |
| D | MachineValueType.h | 90 v128i16 = 42, //128 x i16 enumerator
382 return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 || in is2048BitVector()
468 case v128i16: in getVectorElementType()
565 case v128i16: in getVectorNumElements()
812 case v128i16: in getSizeInBits()
955 if (NumElements == 128) return MVT::v128i16; in getVectorVT()
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| /external/llvm-project/llvm/include/llvm/Support/ |
| D | MachineValueType.h | 91 v128i16 = 43, //128 x i16 enumerator
417 return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 || in is2048BitVector()
537 case v128i16: in getVectorElementType()
660 case v128i16: in getVectorNumElements()
954 case v128i16: in getSizeInBits()
1142 if (NumElements == 128) return MVT::v128i16; in getVectorVT()
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| /external/llvm/lib/IR/ |
| D | ValueTypes.cpp | 169 case MVT::v128i16: return "v128i16"; in getEVTString()
247 case MVT::v128i16: return VectorType::get(Type::getInt16Ty(Context), 128); in getTypeForEVT()
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| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | sve-fixed-length-int-reduce.ll | 175 %res = call i16 @llvm.vector.reduce.add.v128i16(<128 x i16> %op)
483 %res = call i16 @llvm.vector.reduce.smax.v128i16(<128 x i16> %op)
793 %res = call i16 @llvm.vector.reduce.smin.v128i16(<128 x i16> %op)
1103 %res = call i16 @llvm.vector.reduce.umax.v128i16(<128 x i16> %op)
1413 %res = call i16 @llvm.vector.reduce.umin.v128i16(<128 x i16> %op)
1585 declare i16 @llvm.vector.reduce.add.v128i16(<128 x i16>)
1613 declare i16 @llvm.vector.reduce.smax.v128i16(<128 x i16>)
1641 declare i16 @llvm.vector.reduce.smin.v128i16(<128 x i16>)
1669 declare i16 @llvm.vector.reduce.umax.v128i16(<128 x i16>)
1697 declare i16 @llvm.vector.reduce.umin.v128i16(<128 x i16>)
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| D | sve-fixed-length-log-reduce.ll | 184 %res = call i16 @llvm.vector.reduce.and.v128i16(<128 x i16> %op)
507 %res = call i16 @llvm.vector.reduce.xor.v128i16(<128 x i16> %op)
830 %res = call i16 @llvm.vector.reduce.or.v128i16(<128 x i16> %op)
1006 declare i16 @llvm.vector.reduce.and.v128i16(<128 x i16>)
1034 declare i16 @llvm.vector.reduce.or.v128i16(<128 x i16>)
1062 declare i16 @llvm.vector.reduce.xor.v128i16(<128 x i16>)
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| D | sve-fixed-length-int-minmax.ll | 205 %res = call <128 x i16> @llvm.smax.v128i16(<128 x i16> %op1, <128 x i16> %op2)
577 %res = call <128 x i16> @llvm.smin.v128i16(<128 x i16> %op1, <128 x i16> %op2)
950 %res = call <128 x i16> @llvm.umax.v128i16(<128 x i16> %op1, <128 x i16> %op2)
1322 %res = call <128 x i16> @llvm.umin.v128i16(<128 x i16> %op1, <128 x i16> %op2)
1526 declare <128 x i16> @llvm.smin.v128i16(<128 x i16>, <128 x i16>)
1551 declare <128 x i16> @llvm.smax.v128i16(<128 x i16>, <128 x i16>)
1576 declare <128 x i16> @llvm.umin.v128i16(<128 x i16>, <128 x i16>)
1601 declare <128 x i16> @llvm.umax.v128i16(<128 x i16>, <128 x i16>)
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 209 if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_Hexagon_VarArg()
360 (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_HexagonVector()
424 } else if (LocVT == MVT::v256i8 || LocVT == MVT::v128i16 || in RetCC_Hexagon()
547 ty == MVT::v32i64 || ty == MVT::v64i32 || ty == MVT::v128i16 || in IsHvxVectorType()
1141 RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) { in LowerFormalArguments()
1770 addRegisterClass(MVT::v128i16, &Hexagon::VecDblRegs128BRegClass); in HexagonTargetLowering()
2005 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom); in HexagonTargetLowering()
2897 case MVT::v128i16: in getRegForInlineAsmConstraint()
3033 case MVT::v128i16: in allowsMisalignedMemoryAccesses()
3072 case MVT::v128i16: in findRepresentativeClass()
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| D | HexagonRegisterInfo.td | 238 [v256i8,v128i16,v64i32,v32i64], 2048,
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| D | HexagonInstrInfoV60.td | 799 defm : STrivv_pats <v64i16, v128i16>;
874 defm : LDrivv_pats <v64i16, v128i16>;
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 97 case MVT::v128i16: return "MVT::v128i16"; in getEnumName()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ValueTypes.cpp | 187 case MVT::v128i16: return VectorType::get(Type::getInt16Ty(Context), 128); in getTypeForEVT()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 65 def v128i16: ValueType<2048,42>; //128 x i16 vector value
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 67 def v128i16: ValueType<2048,43>; //128 x i16 vector value
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | ValueTypes.cpp | 254 case MVT::v128i16: in getTypeForEVT()
|
| /external/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenTarget.cpp | 109 case MVT::v128i16: return "MVT::v128i16"; in getEnumName()
|
| /external/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 195 def llvm_v128i16_ty : LLVMType<v128i16>; //128 x i16
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | Intrinsics.td | 255 def llvm_v128i16_ty : LLVMType<v128i16>; //128 x i16
|