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Searched refs:v16i16 (Results 1 – 25 of 213) sorted by relevance

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/external/clang/test/CodeGen/
Dppc64-vector.c8 typedef short v16i16 __attribute__((vector_size (32))); typedef
10 struct v16i16 { v16i16 x; }; argument
43 v16i16 test_v16i16(v16i16 x) in test_v16i16()
49 struct v16i16 test_struct_v16i16(struct v16i16 x) in test_struct_v16i16()
/external/llvm-project/clang/test/CodeGen/
Dppc64-vector.c8 typedef short v16i16 __attribute__((vector_size (32))); typedef
10 struct v16i16 { v16i16 x; }; argument
43 v16i16 test_v16i16(v16i16 x) in test_v16i16()
49 struct v16i16 test_struct_v16i16(struct v16i16 x) in test_struct_v16i16()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp388 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
389 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost()
390 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
391 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
414 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. in getArithmeticInstrCost()
415 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. in getArithmeticInstrCost()
418 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. in getArithmeticInstrCost()
419 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. in getArithmeticInstrCost()
451 { ISD::SHL, MVT::v16i16, 1 }, // psllw. in getArithmeticInstrCost()
452 { ISD::SRL, MVT::v16i16, 1 }, // psrlw. in getArithmeticInstrCost()
[all …]
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
122 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
165 if (ISD == ISD::SHL && LT.second == MVT::v16i16 && in getArithmeticInstrCost()
194 { ISD::SHL, MVT::v16i16, 2 }, in getArithmeticInstrCost()
195 { ISD::SRL, MVT::v16i16, 4 }, in getArithmeticInstrCost()
196 { ISD::SRA, MVT::v16i16, 4 }, in getArithmeticInstrCost()
213 { ISD::SHL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. in getArithmeticInstrCost()
216 { ISD::SRL, MVT::v16i16, 10 }, // extend/vpsrlvd/pack sequence. in getArithmeticInstrCost()
219 { ISD::SRA, MVT::v16i16, 10 }, // extend/vpsravd/pack sequence. in getArithmeticInstrCost()
225 { ISD::SDIV, MVT::v16i16, 16*20 }, in getArithmeticInstrCost()
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp432 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
433 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost()
434 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
435 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence in getArithmeticInstrCost()
458 { ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split. in getArithmeticInstrCost()
459 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split. in getArithmeticInstrCost()
462 { ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split. in getArithmeticInstrCost()
463 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split. in getArithmeticInstrCost()
498 { ISD::SHL, MVT::v16i16, 1 }, // vpsllvw in getArithmeticInstrCost()
499 { ISD::SRL, MVT::v16i16, 1 }, // vpsrlvw in getArithmeticInstrCost()
[all …]
/external/llvm-project/llvm/test/Verifier/
Dextract-vector-mismatched-element-types.ll5 …%retval = call <16 x i16> @llvm.experimental.vector.extract.v16i16.nxv16i8(<vscale x 16 x i8> %vec…
9 declare <16 x i16> @llvm.experimental.vector.extract.v16i16.nxv16i8(<vscale x 16 x i8>, i64)
/external/llvm-project/llvm/test/CodeGen/AArch64/
Daarch64-minmaxv.ll134 declare i16 @llvm.vector.reduce.umax.v16i16(<16 x i16>)
141 %r = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> %arr.load)
158 declare i16 @llvm.vector.reduce.umin.v16i16(<16 x i16>)
165 %r = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %arr.load)
182 declare i16 @llvm.vector.reduce.smax.v16i16(<16 x i16>)
189 %r = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %arr.load)
206 declare i16 @llvm.vector.reduce.smin.v16i16(<16 x i16>)
213 %r = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %arr.load)
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h82 v16i16 = 34, // 16 x i16 enumerator
258 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 || in is256BitVector()
338 case v16i16: in getVectorElementType()
391 case v16i16: in getVectorNumElements()
491 case v16i16: in getSizeInBits()
618 if (NumElements == 16) return MVT::v16i16; in getVectorVT()
/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Dbswap.ll17 declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>)
114 …an estimated cost of 14 for instruction: %bswap = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %a)
118 … an estimated cost of 2 for instruction: %bswap = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %a)
122 … an estimated cost of 4 for instruction: %bswap = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %a)
126 … an estimated cost of 1 for instruction: %bswap = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %a)
129 %bswap = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %a)
Darith-uminmax.ll23 declare <16 x i16> @llvm.umax.v16i16(<16 x i16>, <16 x i16>)
43 …stimated cost of 4 for instruction: %V16I16 = call <16 x i16> @llvm.umax.v16i16(<16 x i16> undef, …
62 …stimated cost of 4 for instruction: %V16I16 = call <16 x i16> @llvm.umax.v16i16(<16 x i16> undef, …
81 …stimated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.umax.v16i16(<16 x i16> undef, …
100 …stimated cost of 4 for instruction: %V16I16 = call <16 x i16> @llvm.umax.v16i16(<16 x i16> undef, …
119 …stimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.umax.v16i16(<16 x i16> undef, …
138 …stimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.umax.v16i16(<16 x i16> undef, …
157 …stimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.umax.v16i16(<16 x i16> undef, …
176 …stimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.umax.v16i16(<16 x i16> undef, …
196 %V16I16 = call <16 x i16> @llvm.umax.v16i16(<16 x i16> undef, <16 x i16> undef)
[all …]
Darith-sminmax.ll23 declare <16 x i16> @llvm.smax.v16i16(<16 x i16>, <16 x i16>)
43 …stimated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.smax.v16i16(<16 x i16> undef, …
62 …stimated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.smax.v16i16(<16 x i16> undef, …
81 …stimated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.smax.v16i16(<16 x i16> undef, …
100 …stimated cost of 4 for instruction: %V16I16 = call <16 x i16> @llvm.smax.v16i16(<16 x i16> undef, …
119 …stimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.smax.v16i16(<16 x i16> undef, …
138 …stimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.smax.v16i16(<16 x i16> undef, …
157 …stimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.smax.v16i16(<16 x i16> undef, …
176 …stimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.smax.v16i16(<16 x i16> undef, …
196 %V16I16 = call <16 x i16> @llvm.smax.v16i16(<16 x i16> undef, <16 x i16> undef)
[all …]
Darith-usat.ll30 declare <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16>, <16 x i16>)
50 …ated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> undef, …
69 …ated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> undef, …
88 …ated cost of 4 for instruction: %V16I16 = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> undef, …
107 …ated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> undef, …
126 …ated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> undef, …
145 …ated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> undef, …
164 …ated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> undef, …
183 …ated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> undef, …
202 …ated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> undef, …
[all …]
Darith-ssat.ll29 declare <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16>, <16 x i16>)
49 …ated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> undef, …
68 …ated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> undef, …
87 …ated cost of 4 for instruction: %V16I16 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> undef, …
106 …ated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> undef, …
125 …ated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> undef, …
144 …ated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> undef, …
163 …ated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> undef, …
182 …ated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> undef, …
201 …ated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> undef, …
[all …]
Dabs.ll119 …estimated cost of 4 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, …
126 …estimated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, …
133 …estimated cost of 2 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, …
140 …estimated cost of 3 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, …
147 …estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, …
154 …estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, …
161 …estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, …
168 …estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, …
174 %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, i1 0)
351 …estimated cost of 4 for instruction: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> %a256, …
[all …]
/external/llvm/test/CodeGen/X86/
Davx2-cmp.ll18 define <16 x i16> @v16i16-cmp(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
46 define <16 x i16> @v16i16-cmpeq(<16 x i16> %i, <16 x i16> %j) nounwind readnone {
Davx512bw-mov.ll155 …%res = call <16 x i16> @llvm.masked.load.v16i16(<16 x i16>* %addr, i32 4, <16 x i1>%mask, <16 x i1…
158 declare <16 x i16> @llvm.masked.load.v16i16(<16 x i16>*, i32, <16 x i1>, <16 x i16>)
215 call void @llvm.masked.store.v16i16(<16 x i16> %val, <16 x i16>* %addr, i32 4, <16 x i1>%mask)
218 declare void @llvm.masked.store.v16i16(<16 x i16>, <16 x i16>*, i32, <16 x i1>)
/external/llvm-project/llvm/test/CodeGen/X86/
Davx512bwvl-intrinsics-canonical.ll88 %1 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> %a, <16 x i16> %b)
91 declare <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16>, <16 x i16>)
100 %1 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> %a, <16 x i16> %b)
112 %1 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> %a, <16 x i16> %b)
124 %1 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> %a, <16 x i16> %b)
136 %1 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> %a, <16 x i16> %b)
149 %1 = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> %a, <16 x i16> %b)
232 %sub = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> %a, <16 x i16> %b)
235 declare <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16>, <16 x i16>)
244 %sub = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> %a, <16 x i16> %b)
[all …]
Davx512bw-mov.ll148 …%res = call <16 x i16> @llvm.masked.load.v16i16(<16 x i16>* %addr, i32 4, <16 x i1>%mask, <16 x i1…
151 declare <16 x i16> @llvm.masked.load.v16i16(<16 x i16>*, i32, <16 x i1>, <16 x i16>)
205 call void @llvm.masked.store.v16i16(<16 x i16> %val, <16 x i16>* %addr, i32 4, <16 x i1>%mask)
208 declare void @llvm.masked.store.v16i16(<16 x i16>, <16 x i16>*, i32, <16 x i1>)
Dbitcast-setcc-256.ll9 define i16 @v16i16(<16 x i16> %a, <16 x i16> %b) {
10 ; SSE2-SSSE3-LABEL: v16i16:
19 ; AVX1-LABEL: v16i16:
31 ; AVX2-LABEL: v16i16:
41 ; AVX512F-LABEL: v16i16:
51 ; AVX512BW-LABEL: v16i16:
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h87 v16i16 = 39, // 16 x i16 enumerator
361 SimpleTy == MVT::v16i16 || SimpleTy == MVT::v8i32 || in is256BitVector()
465 case v16i16: in getVectorElementType()
587 case v16i16: in getVectorNumElements()
778 case v16i16: in getSizeInBits()
952 if (NumElements == 16) return MVT::v16i16; in getVectorVT()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc1519 …{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPADDWYrr:{ *:[v16i16…
1530 …:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPADDWZ256rr:{ *:[v16i…
2063 …{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPSUBWYrr:{ *:[v16i16…
2074 …:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPSUBWZ256rr:{ *:[v16i…
2490 …{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPMULLWYrr:{ *:[v16i1…
2501 …[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPMULLWZ256rr:{ *:[v16i…
3857 …:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPANDYrr:{ *:[v16i16…
3868 …{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VANDPSYrr:{ *:[v16i16…
3879 …:[v16i16] } VR256X:{ *:[v16i16] }:$src1, VR256X:{ *:[v16i16] }:$src2) => (VPANDQZ256rr:{ *:[v16i…
5431 …:{ *:[v16i16] } VR256:{ *:[v16i16] }:$src1, VR256:{ *:[v16i16] }:$src2) => (VPORYrr:{ *:[v16i16]…
[all …]
/external/llvm-project/llvm/test/Instrumentation/MemorySanitizer/
Dabs-vector.ll40 ; CHECK-NEXT: [[TMP4:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP3]], i1 false)
49 %1 = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> %0, i1 false)
93 declare <16 x i16> @llvm.abs.v16i16(<16 x i16>, i1 immarg) #1
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dmve-vaddv.ll8 declare i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16>)
65 %r = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %s1)
151 %t = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %s1)
/external/llvm/test/Analysis/CostModel/X86/
Dctbits-cost.ll17 declare <16 x i16> @llvm.ctpop.v16i16(<16 x i16>)
70 %ctpop = call <16 x i16> @llvm.ctpop.v16i16(<16 x i16> %a)
101 declare <16 x i16> @llvm.ctlz.v16i16(<16 x i16>, i1)
199 %ctlz = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> %a, i1 0)
208 %ctlz = call <16 x i16> @llvm.ctlz.v16i16(<16 x i16> %a, i1 1)
257 declare <16 x i16> @llvm.cttz.v16i16(<16 x i16>, i1)
355 %cttz = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> %a, i1 0)
364 %cttz = call <16 x i16> @llvm.cttz.v16i16(<16 x i16> %a, i1 1)
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h88 v16i16 = 40, // 16 x i16 enumerator
392 SimpleTy == MVT::v32i8 || SimpleTy == MVT::v16i16 || in is256BitVector()
534 case v16i16: in getVectorElementType()
695 case v16i16: in getVectorNumElements()
912 case v16i16: in getSizeInBits()
1139 if (NumElements == 16) return MVT::v16i16; in getVectorVT()

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