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/external/llvm-project/llvm/test/CodeGen/AArch64/
Dfpconv-vector-op-scalarize-strict.ll15 …%0 = call <1 x double> @llvm.experimental.constrained.sitofp.v1f64.v1i1(<1 x i1> %in, metadata !"r…
26 …%0 = call <1 x double> @llvm.experimental.constrained.uitofp.v1f64.v1i1(<1 x i1> %in, metadata !"r…
32 declare <1 x double> @llvm.experimental.constrained.sitofp.v1f64.v1i1(<1 x i1>, metadata, metadata)
33 declare <1 x double> @llvm.experimental.constrained.uitofp.v1f64.v1i1(<1 x i1>, metadata, metadata)
Daarch64-neon-v1i1-setcc.ll2 ; arm64 has a separate copy as aarch64-neon-v1i1-setcc.ll
4 ; This file test the DAG node like "v1i1 SETCC v1i64, v1i64". As the v1i1 type
10 ; "v1i1 SETCC" correctly, these test cases are not needed.
Dvecreduce-bool.ll4 declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
11 declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %a)
27 %y = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %x)
122 %y = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> %x)
Darm64-vector-ext.ll18 ; Extend from v1i1 was crashing things (PR20791). Make sure we do something
Dvecreduce-add-legalization.ll4 declare i1 @llvm.vector.reduce.add.v1i1(<1 x i1> %a)
25 %b = call i1 @llvm.vector.reduce.add.v1i1(<1 x i1> %a)
Dvecreduce-umax-legalization.ll4 declare i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> %a)
26 %b = call i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> %a)
Dvecreduce-and-legalization.ll4 declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
25 %b = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
Dtrunc-v1i64.ll65 ; PR20777: v1i1 is also problematic, but we can't widen it, so we extract_elt
/external/llvm/test/CodeGen/AArch64/
Daarch64-neon-v1i1-setcc.ll2 ; arm64 has a separate copy as aarch64-neon-v1i1-setcc.ll
4 ; This file test the DAG node like "v1i1 SETCC v1i64, v1i64". As the v1i1 type
10 ; "v1i1 SETCC" correctly, these test cases are not needed.
Darm64-vector-ext.ll18 ; Extend from v1i1 was crashing things (PR20791). Make sure we do something
Dtrunc-v1i64.ll65 ; PR20777: v1i1 is also problematic, but we can't widen it, so we extract_elt
/external/llvm/test/CodeGen/X86/
Dpr28444.ll7 ; i8 = extract_vector_elt v1i1, Constant:i64<0>
8 ; i1 = extract_vector_elt v1i1, Constant:i64<0>
/external/llvm-project/llvm/test/CodeGen/X86/
Dpr28444.ll8 ; i8 = extract_vector_elt v1i1, Constant:i64<0>
9 ; i1 = extract_vector_elt v1i1, Constant:i64<0>
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h60 v1i1 = 14, // 1 x i1 enumerator
116 FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
147 FIRST_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
207 FIRST_VECTOR_VALUETYPE = v1i1,
428 case v1i1: in getVectorElementType()
652 case v1i1: in getVectorNumElements()
699 case v1i1: return TypeSize::Fixed(1); in getSizeInBits()
923 if (NumElements == 1) return MVT::v1i1; in getVectorVT()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallingConv.td81 // Promote i1/i8/i16/v1i1 arguments to i32.
82 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
155 // Promote i1, v1i1, v8i1 arguments to i8.
156 CCIfType<[i1, v1i1, v8i1], CCPromoteToType<i8>>,
216 CCIfType<[v1i1], CCPromoteToType<i8>>,
390 CCIfType<[v1i1], CCPromoteToType<i8>>,
504 // Promote i1/i8/i16/v1i1 arguments to i32.
505 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
605 // Promote i1/v1i1 arguments to i8.
606 CCIfType<[i1, v1i1], CCPromoteToType<i8>>,
[all …]
DX86InstrVecCompiler.td167 def maskzeroupperv1i1 : maskzeroupper<v1i1, VK1>;
254 (v1i1 VK1:$mask), (iPTR 0))),
282 (v1i1 VK1:$mask), (iPTR 0))),
332 (v1i1 VK1:$mask), (iPTR 0))),
345 (v1i1 VK1:$mask), (iPTR 0))),
/external/llvm-project/llvm/lib/Target/X86/
DX86CallingConv.td81 // Promote i1/i8/i16/v1i1 arguments to i32.
82 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
155 // Promote i1, v1i1, v8i1 arguments to i8.
156 CCIfType<[i1, v1i1, v8i1], CCPromoteToType<i8>>,
216 CCIfType<[v1i1], CCPromoteToType<i8>>,
393 CCIfType<[v1i1], CCPromoteToType<i8>>,
507 // Promote i1/i8/i16/v1i1 arguments to i32.
508 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
611 // Promote i1/v1i1 arguments to i8.
612 CCIfType<[i1, v1i1], CCPromoteToType<i8>>,
[all …]
DX86InstrVecCompiler.td167 def maskzeroupperv1i1 : maskzeroupper<v1i1, VK1>;
254 (v1i1 VK1:$mask), (iPTR 0))),
282 (v1i1 VK1:$mask), (iPTR 0))),
332 (v1i1 VK1:$mask), (iPTR 0))),
345 (v1i1 VK1:$mask), (iPTR 0))),
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h61 v1i1 = 15, // 1 x i1 enumerator
120 FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
166 FIRST_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
234 FIRST_VECTOR_VALUETYPE = v1i1,
495 case v1i1: in getVectorElementType()
770 case v1i1: in getVectorNumElements()
823 case v1i1: return TypeSize::Fixed(1); in getSizeInBits()
1110 if (NumElements == 1) return MVT::v1i1; in getVectorVT()
/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Dreduce-xor.ll157 … an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
168 … an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
179 … an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
190 … an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
201 … an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
212 … an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
223 … an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
234 … an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
244 %V1 = call i1 @llvm.vector.reduce.xor.v1i1(<1 x i1> undef)
282 declare i1 @llvm.vector.reduce.xor.v1i1(<1 x i1>)
Dreduce-and.ll157 … an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> undef)
168 … an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> undef)
179 … an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> undef)
190 … an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> undef)
201 … an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> undef)
212 … an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> undef)
222 %V1 = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> undef)
260 declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1>)
Dreduce-or.ll157 …d an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef)
168 …d an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef)
179 …d an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef)
190 …d an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef)
201 …d an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef)
212 …d an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef)
222 %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef)
260 declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1>)
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenCallingConv.inc385 LocVT == MVT::v1i1) {
571 LocVT == MVT::v1i1) {
767 LocVT == MVT::v1i1) {
810 LocVT == MVT::v1i1) {
1073 LocVT == MVT::v1i1) {
1097 LocVT == MVT::v1i1) {
1390 LocVT == MVT::v1i1) {
1876 LocVT == MVT::v1i1) {
2143 LocVT == MVT::v1i1) {
2347 LocVT == MVT::v1i1) {
[all …]
DX86GenGlobalISel.inc2581 …v1i1] } (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] }), VK1:{ *:[v1i1] }:$src2) => (…
2615 …v1i1] } VK1:{ *:[v1i1] }:$src2, (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] })) => (…
2643 …v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KANDW…
4037 …v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KORWr…
5618 …v1i1] } (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] }), VK1:{ *:[v1i1] }:$src2) => (…
5652 …v1i1] } (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2), -1:{ *:[v1i1] }) => (…
5686 …v1i1] } VK1:{ *:[v1i1] }:$src2, (xor:{ *:[v1i1] } VK1:{ *:[v1i1] }:$src1, -1:{ *:[v1i1] })) => (…
5714 …v1i1] } VK1:{ *:[v1i1] }:$src1, VK1:{ *:[v1i1] }:$src2) => (COPY_TO_REGCLASS:{ *:[v1i1] } (KXORW…
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp159 case MVT::v1i1: return VectorType::get(Type::getInt1Ty(Context), 1); in getTypeForEVT()

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