1; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py 2; RUN: opt < %s -cost-model -mtriple=x86_64-apple-darwin -analyze -mattr=+sse2 | FileCheck %s --check-prefixes=SSE 3; RUN: opt < %s -cost-model -mtriple=x86_64-apple-darwin -analyze -mattr=+ssse3 | FileCheck %s --check-prefixes=SSE 4; RUN: opt < %s -cost-model -mtriple=x86_64-apple-darwin -analyze -mattr=+sse4.2 | FileCheck %s --check-prefixes=SSE 5; RUN: opt < %s -cost-model -mtriple=x86_64-apple-darwin -analyze -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1 6; RUN: opt < %s -cost-model -mtriple=x86_64-apple-darwin -analyze -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2 7; RUN: opt < %s -cost-model -mtriple=x86_64-apple-darwin -analyze -mattr=+avx512f | FileCheck %s --check-prefixes=AVX512,AVX512F 8; RUN: opt < %s -cost-model -mtriple=x86_64-apple-darwin -analyze -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX512,AVX512BW 9; RUN: opt < %s -cost-model -mtriple=x86_64-apple-darwin -analyze -mattr=+avx512f,+avx512dq | FileCheck %s --check-prefixes=AVX512,AVX512DQ 10 11define i32 @reduce_i64(i32 %arg) { 12; SSE-LABEL: 'reduce_i64' 13; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> undef) 14; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> undef) 15; SSE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> undef) 16; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> undef) 17; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V16 = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> undef) 18; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 19; 20; AVX-LABEL: 'reduce_i64' 21; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> undef) 22; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> undef) 23; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> undef) 24; AVX-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> undef) 25; AVX-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> undef) 26; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 27; 28; AVX512-LABEL: 'reduce_i64' 29; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> undef) 30; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> undef) 31; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> undef) 32; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> undef) 33; AVX512-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> undef) 34; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 35; 36 %V1 = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> undef) 37 %V2 = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> undef) 38 %V4 = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> undef) 39 %V8 = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> undef) 40 %V16 = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> undef) 41 ret i32 undef 42} 43 44define i32 @reduce_i32(i32 %arg) { 45; SSE-LABEL: 'reduce_i32' 46; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> undef) 47; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> undef) 48; SSE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V8 = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> undef) 49; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> undef) 50; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V32 = call i32 @llvm.vector.reduce.or.v32i32(<32 x i32> undef) 51; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 52; 53; AVX-LABEL: 'reduce_i32' 54; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> undef) 55; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> undef) 56; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> undef) 57; AVX-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> undef) 58; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.or.v32i32(<32 x i32> undef) 59; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 60; 61; AVX512-LABEL: 'reduce_i32' 62; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> undef) 63; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> undef) 64; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> undef) 65; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> undef) 66; AVX512-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i32 @llvm.vector.reduce.or.v32i32(<32 x i32> undef) 67; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 68; 69 %V2 = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> undef) 70 %V4 = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> undef) 71 %V8 = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> undef) 72 %V16 = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> undef) 73 %V32 = call i32 @llvm.vector.reduce.or.v32i32(<32 x i32> undef) 74 ret i32 undef 75} 76 77define i32 @reduce_i16(i32 %arg) { 78; SSE-LABEL: 'reduce_i16' 79; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> undef) 80; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> undef) 81; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> undef) 82; SSE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16 = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> undef) 83; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.vector.reduce.or.v32i16(<32 x i16> undef) 84; SSE-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V64 = call i16 @llvm.vector.reduce.or.v64i16(<64 x i16> undef) 85; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 86; 87; AVX-LABEL: 'reduce_i16' 88; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> undef) 89; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> undef) 90; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> undef) 91; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> undef) 92; AVX-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i16 @llvm.vector.reduce.or.v32i16(<32 x i16> undef) 93; AVX-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.vector.reduce.or.v64i16(<64 x i16> undef) 94; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 95; 96; AVX512-LABEL: 'reduce_i16' 97; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> undef) 98; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> undef) 99; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> undef) 100; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> undef) 101; AVX512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i16 @llvm.vector.reduce.or.v32i16(<32 x i16> undef) 102; AVX512-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i16 @llvm.vector.reduce.or.v64i16(<64 x i16> undef) 103; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 104; 105 %V2 = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> undef) 106 %V4 = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> undef) 107 %V8 = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> undef) 108 %V16 = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> undef) 109 %V32 = call i16 @llvm.vector.reduce.or.v32i16(<32 x i16> undef) 110 %V64 = call i16 @llvm.vector.reduce.or.v64i16(<64 x i16> undef) 111 ret i32 undef 112} 113 114define i32 @reduce_i8(i32 %arg) { 115; SSE-LABEL: 'reduce_i8' 116; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.or.v2i8(<2 x i8> undef) 117; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> undef) 118; SSE-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> undef) 119; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> undef) 120; SSE-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> undef) 121; SSE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.vector.reduce.or.v64i8(<64 x i8> undef) 122; SSE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> undef) 123; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 124; 125; AVX-LABEL: 'reduce_i8' 126; AVX-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.or.v2i8(<2 x i8> undef) 127; AVX-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> undef) 128; AVX-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> undef) 129; AVX-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> undef) 130; AVX-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> undef) 131; AVX-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i8 @llvm.vector.reduce.or.v64i8(<64 x i8> undef) 132; AVX-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> undef) 133; AVX-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 134; 135; AVX512-LABEL: 'reduce_i8' 136; AVX512-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i8 @llvm.vector.reduce.or.v2i8(<2 x i8> undef) 137; AVX512-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> undef) 138; AVX512-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> undef) 139; AVX512-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> undef) 140; AVX512-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> undef) 141; AVX512-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i8 @llvm.vector.reduce.or.v64i8(<64 x i8> undef) 142; AVX512-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> undef) 143; AVX512-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 144; 145 %V2 = call i8 @llvm.vector.reduce.or.v2i8(<2 x i8> undef) 146 %V4 = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> undef) 147 %V8 = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> undef) 148 %V16 = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> undef) 149 %V32 = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> undef) 150 %V64 = call i8 @llvm.vector.reduce.or.v64i8(<64 x i8> undef) 151 %V128 = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> undef) 152 ret i32 undef 153} 154 155define i32 @reduce_i1(i32 %arg) { 156; SSE-LABEL: 'reduce_i1' 157; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef) 158; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef) 159; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> undef) 160; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> undef) 161; SSE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> undef) 162; SSE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef) 163; SSE-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef) 164; SSE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef) 165; SSE-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 166; 167; AVX1-LABEL: 'reduce_i1' 168; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef) 169; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef) 170; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> undef) 171; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> undef) 172; AVX1-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> undef) 173; AVX1-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef) 174; AVX1-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef) 175; AVX1-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef) 176; AVX1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 177; 178; AVX2-LABEL: 'reduce_i1' 179; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef) 180; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef) 181; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> undef) 182; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> undef) 183; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> undef) 184; AVX2-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef) 185; AVX2-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef) 186; AVX2-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef) 187; AVX2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 188; 189; AVX512F-LABEL: 'reduce_i1' 190; AVX512F-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef) 191; AVX512F-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef) 192; AVX512F-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> undef) 193; AVX512F-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> undef) 194; AVX512F-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> undef) 195; AVX512F-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef) 196; AVX512F-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef) 197; AVX512F-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef) 198; AVX512F-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 199; 200; AVX512BW-LABEL: 'reduce_i1' 201; AVX512BW-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef) 202; AVX512BW-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef) 203; AVX512BW-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> undef) 204; AVX512BW-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> undef) 205; AVX512BW-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> undef) 206; AVX512BW-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef) 207; AVX512BW-NEXT: Cost Model: Found an estimated cost of 13 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef) 208; AVX512BW-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef) 209; AVX512BW-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 210; 211; AVX512DQ-LABEL: 'reduce_i1' 212; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef) 213; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef) 214; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V4 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> undef) 215; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8 = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> undef) 216; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V16 = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> undef) 217; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef) 218; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef) 219; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef) 220; AVX512DQ-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef 221; 222 %V1 = call i1 @llvm.vector.reduce.or.v1i1(<1 x i1> undef) 223 %V2 = call i1 @llvm.vector.reduce.or.v2i1(<2 x i1> undef) 224 %V4 = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> undef) 225 %V8 = call i1 @llvm.vector.reduce.or.v8i1(<8 x i1> undef) 226 %V16 = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> undef) 227 %V32 = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> undef) 228 %V64 = call i1 @llvm.vector.reduce.or.v64i1(<64 x i1> undef) 229 %V128 = call i1 @llvm.vector.reduce.or.v128i1(<128 x i1> undef) 230 ret i32 undef 231} 232 233declare i64 @llvm.vector.reduce.or.v1i64(<1 x i64>) 234declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>) 235declare i64 @llvm.vector.reduce.or.v4i64(<4 x i64>) 236declare i64 @llvm.vector.reduce.or.v8i64(<8 x i64>) 237declare i64 @llvm.vector.reduce.or.v16i64(<16 x i64>) 238 239declare i32 @llvm.vector.reduce.or.v2i32(<2 x i32>) 240declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>) 241declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32>) 242declare i32 @llvm.vector.reduce.or.v16i32(<16 x i32>) 243declare i32 @llvm.vector.reduce.or.v32i32(<32 x i32>) 244 245declare i16 @llvm.vector.reduce.or.v2i16(<2 x i16>) 246declare i16 @llvm.vector.reduce.or.v4i16(<4 x i16>) 247declare i16 @llvm.vector.reduce.or.v8i16(<8 x i16>) 248declare i16 @llvm.vector.reduce.or.v16i16(<16 x i16>) 249declare i16 @llvm.vector.reduce.or.v32i16(<32 x i16>) 250declare i16 @llvm.vector.reduce.or.v64i16(<64 x i16>) 251 252declare i8 @llvm.vector.reduce.or.v2i8(<2 x i8>) 253declare i8 @llvm.vector.reduce.or.v4i8(<4 x i8>) 254declare i8 @llvm.vector.reduce.or.v8i8(<8 x i8>) 255declare i8 @llvm.vector.reduce.or.v16i8(<16 x i8>) 256declare i8 @llvm.vector.reduce.or.v32i8(<32 x i8>) 257declare i8 @llvm.vector.reduce.or.v64i8(<64 x i8>) 258declare i8 @llvm.vector.reduce.or.v128i8(<128 x i8>) 259 260declare i1 @llvm.vector.reduce.or.v1i1(<1 x i1>) 261declare i1 @llvm.vector.reduce.or.v2i1(<2 x i1>) 262declare i1 @llvm.vector.reduce.or.v4i1(<4 x i1>) 263declare i1 @llvm.vector.reduce.or.v8i1(<8 x i1>) 264declare i1 @llvm.vector.reduce.or.v16i1(<16 x i1>) 265declare i1 @llvm.vector.reduce.or.v32i1(<32 x i1>) 266declare i1 @llvm.vector.reduce.or.v64i1(<64 x i1>) 267declare i1 @llvm.vector.reduce.or.v128i1(<128 x i1>) 268