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Searched refs:v1i16 (Results 1 – 25 of 52) sorted by relevance

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/external/clang/test/CodeGen/
Dsystemz-abi-vector.c13 typedef __attribute__((vector_size(2))) short v1i16; typedef
66 v1i16 pass_v1i16(v1i16 arg) { return arg; } in pass_v1i16()
/external/llvm-project/clang/test/CodeGen/SystemZ/
Dsystemz-abi-vector.c23 typedef __attribute__((vector_size(2))) short v1i16; typedef
76 v1i16 pass_v1i16(v1i16 arg) { return arg; } in pass_v1i16()
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h78 v1i16 = 30, // 1 x i16 enumerator
228 return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 || in is16BitVector()
334 case v1i16: in getVectorElementType()
420 case v1i16: in getVectorNumElements()
458 case v1i16: return 16; in getSizeInBits()
614 if (NumElements == 1) return MVT::v1i16; in getVectorVT()
DValueTypes.td55 def v1i16 : ValueType<16 , 30>; // 1 x i16 vector value
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h82 v1i16 = 34, // 1 x i16 enumerator
329 return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 || in is16BitVector()
460 case v1i16: in getVectorElementType()
654 case v1i16: in getVectorNumElements()
714 case v1i16: return TypeSize::Fixed(16); in getSizeInBits()
947 if (NumElements == 1) return MVT::v1i16; in getVectorVT()
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dtrunc-v1i64.ll6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
12 ; Just like v1i16 and v1i8, there is no XTN generated.
Dvecreduce-add-legalization.ll6 declare i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %a)
45 %b = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %a)
Dvecreduce-umax-legalization.ll6 declare i16 @llvm.vector.reduce.umax.v1i16(<1 x i16> %a)
46 %b = call i16 @llvm.vector.reduce.umax.v1i16(<1 x i16> %a)
Dvecreduce-and-legalization.ll6 declare i16 @llvm.vector.reduce.and.v1i16(<1 x i16> %a)
45 %b = call i16 @llvm.vector.reduce.and.v1i16(<1 x i16> %a)
Dssub_sat_vec.ll13 declare <1 x i16> @llvm.ssub.sat.v1i16(<1 x i16>, <1 x i16>)
256 define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
257 ; CHECK-LABEL: v1i16:
266 %z = call <1 x i16> @llvm.ssub.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
Dusub_sat_vec.ll13 declare <1 x i16> @llvm.usub.sat.v1i16(<1 x i16>, <1 x i16>)
256 define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
257 ; CHECK-LABEL: v1i16:
266 %z = call <1 x i16> @llvm.usub.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
Duadd_sat_vec.ll13 declare <1 x i16> @llvm.uadd.sat.v1i16(<1 x i16>, <1 x i16>)
255 define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
256 ; CHECK-LABEL: v1i16:
265 %z = call <1 x i16> @llvm.uadd.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
Dsadd_sat_vec.ll13 declare <1 x i16> @llvm.sadd.sat.v1i16(<1 x i16>, <1 x i16>)
255 define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
256 ; CHECK-LABEL: v1i16:
265 %z = call <1 x i16> @llvm.sadd.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
/external/llvm/test/CodeGen/AArch64/
Dtrunc-v1i64.ll6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
12 ; Just like v1i16 and v1i8, there is no XTN generated.
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h83 v1i16 = 35, // 1 x i16 enumerator
358 return (SimpleTy == MVT::v2i8 || SimpleTy == MVT::v1i16 || in is16BitVector()
529 case v1i16: in getVectorElementType()
772 case v1i16: in getVectorNumElements()
839 case v1i16: return TypeSize::Fixed(16); in getSizeInBits()
1134 if (NumElements == 1) return MVT::v1i16; in getVectorVT()
/external/llvm/lib/IR/
DValueTypes.cpp162 case MVT::v1i16: return "v1i16"; in getEVTString()
240 case MVT::v1i16: return VectorType::get(Type::getInt16Ty(Context), 1); in getTypeForEVT()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SchedFalkorDetails.td681 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
683 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v2…
685 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QSUB(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
690 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v…
694 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQABS(v1i8|v1i16|v1i32|v1i64|v2i32|v4i16|v8i8)$"…
695 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v1i8|v1i16|v1i32|v1i64)$")>;
703 … (instregex "^SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>;
707 … (instregex "^SQRDML(A|S)H(i16|i32|v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>;
DAArch64SchedA57.td348 // D form - v1i8, v1i16, v1i32, v1i64
375 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v…
411 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
501 // D form - v1i8, v1i16, v1i32, v1i64
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedFalkorDetails.td681 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
683 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v2…
685 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QSUB(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
690 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v…
694 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQABS(v1i8|v1i16|v1i32|v1i64|v2i32|v4i16|v8i8)$"…
695 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v1i8|v1i16|v1i32|v1i64)$")>;
703 … (instregex "^SQR?DMULH(v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>;
707 … (instregex "^SQRDML(A|S)H(i16|i32|v8i8|v4i16|v1i32|v2i32|v1i16)(_indexed)?$")>;
DAArch64SchedA57.td347 // D form - v1i8, v1i16, v1i32, v1i64
374 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v…
410 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
500 // D form - v1i8, v1i16, v1i32, v1i64
/external/llvm/test/CodeGen/ARM/
Dcttz_vector.ll11 declare <1 x i16> @llvm.cttz.v1i16(<1 x i16>, i1)
82 %tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 false)
266 %tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 true)
/external/llvm/lib/Target/AArch64/
DAArch64SchedA57.td344 // D form - v1i8, v1i16, v1i32, v1i64
371 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v…
407 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
497 // D form - v1i8, v1i16, v1i32, v1i64
/external/llvm-project/llvm/test/CodeGen/ARM/
Dcttz_vector.ll12 declare <1 x i16> @llvm.cttz.v1i16(<1 x i16>, i1)
129 %tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 false)
384 %tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 true)
/external/llvm-project/llvm/test/Analysis/CostModel/ARM/
Dmve-vecreduce-add.ll29 …estimated cost of 1 for instruction: %a0z = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %a0za)
31 …estimated cost of 1 for instruction: %a0s = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %a0sa)
48 … estimated cost of 1 for instruction: %a5 = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> undef)
56 %a0z = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %a0za)
59 %a0s = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %a0sa)
85 %a5 = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> undef)
429 …estimated cost of 1 for instruction: %a0z = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %a0zm)
433 …estimated cost of 1 for instruction: %a0s = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %a0sm)
467 …n estimated cost of 1 for instruction: %a5 = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %a5m)
481 %a0z = call i16 @llvm.vector.reduce.add.v1i16(<1 x i16> %a0zm)
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Duadd_sat_vec.ll19 declare <1 x i16> @llvm.uadd.sat.v1i16(<1 x i16>, <1 x i16>)
454 define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
455 ; SSE-LABEL: v1i16:
464 ; AVX-LABEL: v1i16:
474 %z = call <1 x i16> @llvm.uadd.sat.v1i16(<1 x i16> %x, <1 x i16> %y)

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