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Searched refs:v1i8 (Results 1 – 25 of 52) sorted by relevance

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/external/clang/test/CodeGen/
Dsystemz-abi-vector.c10 typedef __attribute__((vector_size(1))) char v1i8; typedef
42 v1i8 pass_v1i8(v1i8 arg) { return arg; } in pass_v1i8()
133 struct agg_v1i8 { v1i8 a; };
189 v1i8 va_v1i8(__builtin_va_list l) { return __builtin_va_arg(l, v1i8); } in va_v1i8()
/external/llvm-project/clang/test/CodeGen/SystemZ/
Dsystemz-abi-vector.c20 typedef __attribute__((vector_size(1))) char v1i8; typedef
52 v1i8 pass_v1i8(v1i8 arg) { return arg; } in pass_v1i8()
143 struct agg_v1i8 { v1i8 a; };
199 v1i8 va_v1i8(__builtin_va_list l) { return __builtin_va_arg(l, v1i8); } in va_v1i8()
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h68 v1i8 = 21, // 1 x i8 enumerator
325 case v1i8: in getVectorElementType()
419 case v1i8: in getVectorNumElements()
452 case v1i8: in getSizeInBits()
603 if (NumElements == 1) return MVT::v1i8; in getVectorVT()
DValueTypes.td45 def v1i8 : ValueType<16, 21>; // 1 x i8 vector value
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dtrunc-v1i64.ll6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
12 ; Just like v1i16 and v1i8, there is no XTN generated.
Dvecreduce-add-legalization.ll5 declare i8 @llvm.vector.reduce.add.v1i8(<1 x i8> %a)
35 %b = call i8 @llvm.vector.reduce.add.v1i8(<1 x i8> %a)
Dvecreduce-umax-legalization.ll5 declare i8 @llvm.vector.reduce.umax.v1i8(<1 x i8> %a)
36 %b = call i8 @llvm.vector.reduce.umax.v1i8(<1 x i8> %a)
Dvecreduce-and-legalization.ll5 declare i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %a)
35 %b = call i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %a)
Dssub_sat_vec.ll4 declare <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8>, <1 x i8>)
241 define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
242 ; CHECK-LABEL: v1i8:
251 %z = call <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
Dusub_sat_vec.ll4 declare <1 x i8> @llvm.usub.sat.v1i8(<1 x i8>, <1 x i8>)
241 define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
242 ; CHECK-LABEL: v1i8:
251 %z = call <1 x i8> @llvm.usub.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
Duadd_sat_vec.ll4 declare <1 x i8> @llvm.uadd.sat.v1i8(<1 x i8>, <1 x i8>)
240 define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
241 ; CHECK-LABEL: v1i8:
250 %z = call <1 x i8> @llvm.uadd.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
Dsadd_sat_vec.ll4 declare <1 x i8> @llvm.sadd.sat.v1i8(<1 x i8>, <1 x i8>)
240 define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
241 ; CHECK-LABEL: v1i8:
250 %z = call <1 x i8> @llvm.sadd.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
/external/llvm/test/CodeGen/AArch64/
Dtrunc-v1i64.ll6 ; v1i32 trunc v1i64, v1i16 trunc v1i64, v1i8 trunc v1i64.
12 ; Just like v1i16 and v1i8, there is no XTN generated.
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h72 v1i8 = 25, // 1 x i8 enumerator
445 case v1i8: in getVectorElementType()
653 case v1i8: in getVectorNumElements()
706 case v1i8: in getSizeInBits()
936 if (NumElements == 1) return MVT::v1i8; in getVectorVT()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h73 v1i8 = 26, // 1 x i8 enumerator
513 case v1i8: in getVectorElementType()
771 case v1i8: in getVectorNumElements()
830 case v1i8: in getSizeInBits()
1123 if (NumElements == 1) return MVT::v1i8; in getVectorVT()
/external/llvm/lib/IR/
DValueTypes.cpp153 case MVT::v1i8: return "v1i8"; in getEVTString()
231 case MVT::v1i8: return VectorType::get(Type::getInt8Ty(Context), 1); in getTypeForEVT()
/external/llvm/test/CodeGen/ARM/
Dcttz_vector.ll5 declare <1 x i8> @llvm.cttz.v1i8(<1 x i8>, i1)
28 %tmp = call <1 x i8> @llvm.cttz.v1i8(<1 x i8> %a, i1 false)
212 %tmp = call <1 x i8> @llvm.cttz.v1i8(<1 x i8> %a, i1 true)
/external/llvm/lib/Target/AArch64/
DAArch64SchedA57.td344 // D form - v1i8, v1i16, v1i32, v1i64
371 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v…
407 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
497 // D form - v1i8, v1i16, v1i32, v1i64
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SchedFalkorDetails.td681 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
683 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v2…
685 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QSUB(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
690 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v…
694 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQABS(v1i8|v1i16|v1i32|v1i64|v2i32|v4i16|v8i8)$"…
695 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v1i8|v1i16|v1i32|v1i64)$")>;
DAArch64SchedA57.td348 // D form - v1i8, v1i16, v1i32, v1i64
375 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v…
411 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
501 // D form - v1i8, v1i16, v1i32, v1i64
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedFalkorDetails.td681 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
683 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v2…
685 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QSUB(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
690 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v…
694 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQABS(v1i8|v1i16|v1i32|v1i64|v2i32|v4i16|v8i8)$"…
695 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^SQNEG(v1i8|v1i16|v1i32|v1i64)$")>;
DAArch64SchedA57.td347 // D form - v1i8, v1i16, v1i32, v1i64
374 def : InstRW<[A57Write_5cyc_1W], (instregex "^(P?MUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v…
410 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
500 // D form - v1i8, v1i16, v1i32, v1i64
/external/llvm-project/llvm/test/CodeGen/ARM/
Dcttz_vector.ll6 declare <1 x i8> @llvm.cttz.v1i8(<1 x i8>, i1)
36 %tmp = call <1 x i8> @llvm.cttz.v1i8(<1 x i8> %a, i1 false)
295 %tmp = call <1 x i8> @llvm.cttz.v1i8(<1 x i8> %a, i1 true)
/external/llvm-project/llvm/test/CodeGen/X86/
Duadd_sat_vec.ll10 declare <1 x i8> @llvm.uadd.sat.v1i8(<1 x i8>, <1 x i8>)
427 define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
428 ; SSE-LABEL: v1i8:
438 ; AVX-LABEL: v1i8:
449 %z = call <1 x i8> @llvm.uadd.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
Dusub_sat_vec.ll10 declare <1 x i8> @llvm.usub.sat.v1i8(<1 x i8>, <1 x i8>)
427 define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
428 ; SSE-LABEL: v1i8:
438 ; AVX-LABEL: v1i8:
449 %z = call <1 x i8> @llvm.usub.sat.v1i8(<1 x i8> %x, <1 x i8> %y)

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