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Searched refs:v32i64 (Results 1 – 23 of 23) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DMachineValueType.h100 v32i64 = 50, // 32 x i64 enumerator
280 SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64); in is2048BitVector()
354 case v32i64: return i64; in getVectorElementType()
388 case v32i64: return 32; in getVectorNumElements()
511 case v32i64: return 2048; in getSizeInBits()
638 if (NumElements == 32) return MVT::v32i64; in getVectorVT()
DValueTypes.td77 def v32i64 : ValueType<2048,50>; // 32 x i64 vector value
/external/llvm-project/llvm/test/CodeGen/X86/
Davx512-bugfix-26264.ll34 …%res = call <32 x i64> @llvm.masked.load.v32i64.p0v32i64(<32 x i64>* %ptrs, i32 4, <32 x i1> %mask…
38 declare <32 x i64> @llvm.masked.load.v32i64.p0v32i64(<32 x i64>* %ptrs, i32, <32 x i1> %mask, <32 x…
/external/llvm/test/CodeGen/X86/
Davx512-bugfix-26264.ll42 …%res = call <32 x i64> @llvm.masked.load.v32i64.p0v32i64(<32 x i64>* %ptrs, i32 4, <32 x i1> %mask…
46 declare <32 x i64> @llvm.masked.load.v32i64.p0v32i64(<32 x i64>* %ptrs, i32, <32 x i1> %mask, <32 x…
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h112 v32i64 = 62, // 32 x i64 enumerator
383 SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64); in is2048BitVector()
500 case v32i64: in getVectorElementType()
577 case v32i64: in getVectorNumElements()
814 case v32i64: in getSizeInBits()
979 if (NumElements == 32) return MVT::v32i64; in getVectorVT()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h113 v32i64 = 63, // 32 x i64 enumerator
418 SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64 || in is2048BitVector()
569 case v32i64: in getVectorElementType()
682 case v32i64: in getVectorNumElements()
956 case v32i64: in getSizeInBits()
1166 if (NumElements == 32) return MVT::v32i64; in getVectorVT()
/external/llvm/lib/IR/
DValueTypes.cpp182 case MVT::v32i64: return "v32i64"; in getEVTString()
260 case MVT::v32i64: return VectorType::get(Type::getInt64Ty(Context), 32); in getTypeForEVT()
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-fixed-length-int-reduce.ll327 %res = call i64 @llvm.vector.reduce.add.v32i64(<32 x i64> %op)
637 %res = call i64 @llvm.vector.reduce.smax.v32i64(<32 x i64> %op)
947 %res = call i64 @llvm.vector.reduce.smin.v32i64(<32 x i64> %op)
1257 %res = call i64 @llvm.vector.reduce.umax.v32i64(<32 x i64> %op)
1567 %res = call i64 @llvm.vector.reduce.umin.v32i64(<32 x i64> %op)
1599 declare i64 @llvm.vector.reduce.add.v32i64(<32 x i64>)
1627 declare i64 @llvm.vector.reduce.smax.v32i64(<32 x i64>)
1655 declare i64 @llvm.vector.reduce.smin.v32i64(<32 x i64>)
1683 declare i64 @llvm.vector.reduce.umax.v32i64(<32 x i64>)
1711 declare i64 @llvm.vector.reduce.umin.v32i64(<32 x i64>)
Dsve-fixed-length-log-reduce.ll342 %res = call i64 @llvm.vector.reduce.and.v32i64(<32 x i64> %op)
665 %res = call i64 @llvm.vector.reduce.xor.v32i64(<32 x i64> %op)
988 %res = call i64 @llvm.vector.reduce.or.v32i64(<32 x i64> %op)
1020 declare i64 @llvm.vector.reduce.and.v32i64(<32 x i64>)
1048 declare i64 @llvm.vector.reduce.or.v32i64(<32 x i64>)
1076 declare i64 @llvm.vector.reduce.xor.v32i64(<32 x i64>)
Dsve-fixed-length-int-minmax.ll391 %res = call <32 x i64> @llvm.smax.v32i64(<32 x i64> %op1, <32 x i64> %op2)
763 %res = call <32 x i64> @llvm.smin.v32i64(<32 x i64> %op1, <32 x i64> %op2)
1136 %res = call <32 x i64> @llvm.umax.v32i64(<32 x i64> %op1, <32 x i64> %op2)
1508 %res = call <32 x i64> @llvm.umin.v32i64(<32 x i64> %op1, <32 x i64> %op2)
1538 declare <32 x i64> @llvm.smin.v32i64(<32 x i64>, <32 x i64>)
1563 declare <32 x i64> @llvm.smax.v32i64(<32 x i64>, <32 x i64>)
1588 declare <32 x i64> @llvm.umin.v32i64(<32 x i64>, <32 x i64>)
1613 declare <32 x i64> @llvm.umax.v32i64(<32 x i64>, <32 x i64>)
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp209 if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_Hexagon_VarArg()
360 (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 || in CC_HexagonVector()
425 LocVT == MVT::v64i32 || LocVT == MVT::v32i64) { in RetCC_Hexagon()
547 ty == MVT::v32i64 || ty == MVT::v64i32 || ty == MVT::v128i16 || in IsHvxVectorType()
1140 ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 || in LowerFormalArguments()
1772 addRegisterClass(MVT::v32i64, &Hexagon::VecDblRegs128BRegClass); in HexagonTargetLowering()
2007 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i64, Custom); in HexagonTargetLowering()
2899 case MVT::v32i64: in getRegForInlineAsmConstraint()
3039 case MVT::v32i64: in allowsMisalignedMemoryAccesses()
3074 case MVT::v32i64: in findRepresentativeClass()
DHexagonRegisterInfo.td238 [v256i8,v128i16,v64i32,v32i64], 2048,
DHexagonInstrInfoV60.td801 defm : STrivv_pats <v16i64, v32i64>;
876 defm : LDrivv_pats <v16i64, v32i64>;
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp110 case MVT::v32i64: return "MVT::v32i64"; in getEnumName()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DValueTypes.cpp207 case MVT::v32i64: return VectorType::get(Type::getInt64Ty(Context), 32); in getTypeForEVT()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td87 def v32i64 : ValueType<2048,62>; // 32 x i64 vector value
/external/llvm-project/llvm/test/Transforms/LowerMatrixIntrinsics/
Dmultiply-fused-loops.ll266 …%c = call <32 x i64> @llvm.matrix.multiply.v32i64.v8i64.v16i64(<8 x i64> %a, <16 x i64> %b, i32 4,…
272 declare <32 x i64> @llvm.matrix.multiply.v32i64.v8i64.v16i64(<8 x i64>, <16 x i64>, i32, i32, i32)
/external/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td89 def v32i64 : ValueType<2048,63>; // 32 x i64 vector value
/external/llvm-project/llvm/lib/CodeGen/
DValueTypes.cpp294 case MVT::v32i64: in getTypeForEVT()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenTarget.cpp129 case MVT::v32i64: return "MVT::v32i64"; in getEnumName()
/external/llvm/include/llvm/IR/
DIntrinsics.td210 def llvm_v32i64_ty : LLVMType<v32i64>; // 32 x i64
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsics.td270 def llvm_v32i64_ty : LLVMType<v32i64>; // 32 x i64
/external/llvm-project/llvm/include/llvm/IR/
DIntrinsics.td301 def llvm_v32i64_ty : LLVMType<v32i64>; // 32 x i64