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Searched refs:v4bf16 (Results 1 – 25 of 25) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/AArch64/
Daarch64-bf16-ldst-intrinsics.ll72 …%vld1xN = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld1x2.v4bf16.p0bf16(bfloat* …
80 declare { <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld1x2.v4bf16.p0bf16(bfloat*) nounwind
105 …%vld1xN = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld1x3.v4bf16.p…
116 declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld1x3.v4bf16.p0bf16(bfloat*…
143 …at>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld1x4.v4bf16.p0bf16(bfloat* %pt…
156 declare { <4 x bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld1x4.v4bf16.…
198 …%vld2 = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld2.v4bf16.p0v4bf16(<4 x bfloa…
207 declare { <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld2.v4bf16.p0v4bf16(<4 x bfloat>*) nounwi…
235 …%vld2_lane = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld2lane.v4bf16.p0i8(<4 x …
244 declare { <4 x bfloat>, <4 x bfloat> } @llvm.aarch64.neon.ld2lane.v4bf16.p0i8(<4 x bfloat>, <4 x bf…
[all …]
Daarch64-bf16-dotprod-intrinsics.ll10 …%vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x bfloat> %…
34 …%vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x bfloat> %…
60 …%vbfdot3.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x bfloat> %…
154 declare <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float>, <4 x bfloat>, <4 x bfloat>)
Dbf16.ll30 ; Simple store of v4bf16
/external/llvm-project/llvm/test/CodeGen/ARM/
Dbf16-intrinsics-ld-st.ll68 …%vld1xN = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x2.v4bf16.p0bf16(bfloat* %pt…
100 …%vld1xN = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x3.v4bf16.p0bf…
139 …float>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld1x4.v4bf16.p0bf16(bfloat* %pt…
197 %vld2_v = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2.v4bf16.p0i8(i8* %0, i32 2)
237 …%vld2_lane_v = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2lane.v4bf16.p0i8(i8* %2…
277 …%vld3_v = tail call { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld3.v4bf16.p0i8(i…
327 …all { <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld3lane.v4bf16.p0i8(i8* %3, <4 x …
376 … bfloat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld4.v4bf16.p0i8(i8* %0, i32 2)
435 …oat>, <4 x bfloat>, <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld4lane.v4bf16.p0i8(i8* %4, <4 x …
493 …%vld2_dup_v = tail call { <4 x bfloat>, <4 x bfloat> } @llvm.arm.neon.vld2dup.v4bf16.p0i8(i8* %0, …
[all …]
Dbf16-convert-intrinsics.ll7 declare <4 x bfloat> @llvm.arm.neon.vcvtfp2bf.v4bf16(<4 x float>)
15 %vcvtfp2bf1.i.i = call <4 x bfloat> @llvm.arm.neon.vcvtfp2bf.v4bf16(<4 x float> %a)
Darm-bf16-dotprod-intrinsics.ll10 …%vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x bfloat> %a, <…
33 …%vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x bfloat> %a, <…
60 …%vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x bfloat> %a, <…
166 declare <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float>, <4 x bfloat>, <4 x bfloat>)
/external/llvm-project/llvm/lib/Target/ARM/
DARMCallingConv.td33 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
59 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
74 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
94 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
111 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
168 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
186 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
213 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
236 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
DARMCallingConv.cpp217 case MVT::v4bf16: in CC_ARM_AAPCS_Custom_Aggregate()
DARMInstrNEON.td1063 def : Pat<(vector_insert (v4bf16 DPR:$src),
6388 defm : ExtractEltOddF16VMOVH<v4bf16, v8bf16>;
6392 defm : ExtractEltEvenF16<v4bf16, v8bf16>;
6396 def : Pat<(extractelt (v4bf16 DPR:$src), imm_odd:$lane),
6398 (VGETLNu16 (v4bf16 DPR:$src), imm:$lane),
6519 defm : InsertEltF16<bf16, v4bf16, v8bf16>;
6640 def : Pat<(v4bf16 (ARMvduplane (v4bf16 DPR:$Vm), imm:$lane)),
6644 (v8bf16 (VDUPLN16q (v4bf16 (EXTRACT_SUBREG QPR:$src,
6648 def : Pat<(v4bf16 (ARMvdup (bf16 HPR:$src))),
6649 (v4bf16 (VDUPLN16d (INSERT_SUBREG (v4bf16 (IMPLICIT_DEF)),
[all …]
DARMRegisterInfo.td415 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,
436 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,
443 def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,
DARMISelDAGToDAG.cpp2081 case MVT::v4bf16: in SelectVLD()
2226 case MVT::v4bf16: in SelectVST()
2396 case MVT::v4bf16: in SelectVLDSTLane()
2932 case MVT::v4bf16: in SelectVLDDup()
4765 CurDAG->SelectNodeTo(N, ARM::BF16_VCVT, MVT::v4bf16, Ops); in Select()
DARMISelLowering.cpp810 addDRTypeForNEON(MVT::v4bf16); in ARMTargetLowering()
4349 RegVT == MVT::v4bf16) in LowerFormalArguments()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp3543 } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) { in Select()
3570 } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) { in Select()
3597 } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) { in Select()
3624 } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) { in Select()
3651 } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) { in Select()
3678 } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) { in Select()
3705 } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) { in Select()
3732 } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) { in Select()
3759 } else if (VT == MVT::v4i16 || VT == MVT::v4f16 || VT == MVT::v4bf16) { in Select()
3784 VT == MVT::v8f16 || VT == MVT::v4bf16 || VT == MVT::v8bf16) { in Select()
[all …]
DAArch64CallingConvention.td33 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8],
108 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
117 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16],
134 CCIfBigEndian<CCIfType<[v2i32, v2f32, v4i16, v4f16, v4bf16, v8i8],
152 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
229 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
246 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16],
267 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
289 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
DAArch64InstrInfo.td814 (v2f32 V64:$Rd), (v4bf16 V64:$Rn),
815 (v4bf16 (bitconvert
819 (v4bf16 V64:$Rm),
822 (BF16DOTlanev4bf16 (v2f32 V64:$Rd), (v4bf16 V64:$Rn),
2312 defm : VecROLoadPat<ro64, v4bf16, LDRDroW, LDRDroX>;
2463 def : Pat<(v4bf16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
2988 defm : VecROStorePat<ro64, v4bf16, FPR64, STRDroW, STRDroX>;
3097 def : Pat<(store (v4bf16 FPR64:$Rt),
3240 def : Pat<(store (v4bf16 FPR64:$Rt),
3982 def : Pat<(v4bf16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;
[all …]
DAArch64RegisterInfo.td437 v1i64, v4f16, v4bf16],
440 [v8i8, v4i16, v2i32, v1i64, v4f16, v4bf16, v2f32,
DAArch64InstrFormats.td7850 def v4bf16 : BaseSIMDThreeSameVectorBFDot<0, U, asm, ".2s", ".4h", V64,
7851 v2f32, v4bf16>;
7880 def v4bf16 : BaseSIMDThreeSameVectorBF16DotI<0, U, asm, ".2s", ".4h",
7881 ".2h", V64, v2f32, v4bf16>;
DAArch64ISelLowering.cpp243 addDRTypeForNEON(MVT::v4bf16); in AArch64TargetLowering()
9696 VT != MVT::v4bf16) in LowerINSERT_VECTOR_ELT()
9731 VT != MVT::v4bf16) in LowerEXTRACT_VECTOR_ELT()
/external/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h133 v4bf16 = 78, // 4 x bf16 enumerator
375 SimpleTy == MVT::v4bf16 ||SimpleTy == MVT::v2f32 || in is64BitVector()
596 case v4bf16: in getVectorElementType()
735 case v4bf16: in getVectorNumElements()
872 case v4bf16: in getSizeInBits()
1187 if (NumElements == 4) return MVT::v4bf16; in getVectorVT()
/external/llvm-project/llvm/test/Bitcode/
Darm-bf16-upgrade.ll13 …; CHECK-NEXT: %vbfdot1.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x…
68 ; CHECK: declare <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float>, <4 x bfloat>, <4 x bflo…
Daarch64-bf16-upgrade.ll12 …; CHECK-NEXT: %vbfdot1.i = call <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> %r, …
68 ; CHECK: declare <2 x float> @llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float>, <4 x bfloat>, <4 x …
/external/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td106 def v4bf16 : ValueType<64 , 78>; // 4 x bf16 vector value
/external/llvm-project/llvm/lib/CodeGen/
DValueTypes.cpp324 case MVT::v4bf16: in getTypeForEVT()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenTarget.cpp144 case MVT::v4bf16: return "MVT::v4bf16"; in getEnumName()
/external/llvm-project/llvm/include/llvm/IR/
DIntrinsics.td309 def llvm_v4bf16_ty : LLVMType<v4bf16>; // 4 x bfloat (__bf16)