1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple armv8.6a-arm-none-eabi -mattr=+neon,+bf16 -float-abi=hard -verify-machineinstrs < %s -o - | FileCheck %s 3 4define arm_aapcs_vfpcc <2 x float> @test_vbfdot_f32(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %b) { 5; CHECK-LABEL: test_vbfdot_f32: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vdot.bf16 d0, d1, d2 8; CHECK-NEXT: bx lr 9entry: 10 %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %b) #3 11 ret <2 x float> %vbfdot3.i 12} 13 14define <4 x float> @test_vbfdotq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) { 15; CHECK-LABEL: test_vbfdotq_f32: 16; CHECK: @ %bb.0: @ %entry 17; CHECK-NEXT: vdot.bf16 q0, q1, q2 18; CHECK-NEXT: bx lr 19entry: 20 %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) #3 21 ret <4 x float> %vbfdot3.i 22} 23 24define <2 x float> @test_vbfdot_lane_f32(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %b) { 25; CHECK-LABEL: test_vbfdot_lane_f32: 26; CHECK: @ %bb.0: @ %entry 27; CHECK-NEXT: vdot.bf16 d0, d1, d2[0] 28; CHECK-NEXT: bx lr 29entry: 30 %.cast = bitcast <4 x bfloat> %b to <2 x float> 31 %lane = shufflevector <2 x float> %.cast, <2 x float> undef, <2 x i32> zeroinitializer 32 %.cast1 = bitcast <2 x float> %lane to <4 x bfloat> 33 %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %.cast1) #3 34 ret <2 x float> %vbfdot3.i 35} 36 37define <4 x float> @test_vbfdotq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) { 38; CHECK-LABEL: test_vbfdotq_laneq_f32: 39; CHECK: @ %bb.0: @ %entry 40; CHECK-NEXT: vdup.32 q8, d5[1] 41; CHECK-NEXT: vdot.bf16 q0, q1, q8 42; CHECK-NEXT: bx lr 43entry: 44 %.cast = bitcast <8 x bfloat> %b to <4 x float> 45 %lane = shufflevector <4 x float> %.cast, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> 46 %.cast1 = bitcast <4 x float> %lane to <8 x bfloat> 47 %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %.cast1) #3 48 ret <4 x float> %vbfdot3.i 49} 50 51define <2 x float> @test_vbfdot_laneq_f32(<2 x float> %r, <4 x bfloat> %a, <8 x bfloat> %b) { 52; CHECK-LABEL: test_vbfdot_laneq_f32: 53; CHECK: @ %bb.0: @ %entry 54; CHECK-NEXT: vdot.bf16 d0, d1, d3[1] 55; CHECK-NEXT: bx lr 56entry: 57 %.cast = bitcast <8 x bfloat> %b to <4 x float> 58 %lane = shufflevector <4 x float> %.cast, <4 x float> undef, <2 x i32> <i32 3, i32 3> 59 %.cast1 = bitcast <2 x float> %lane to <4 x bfloat> 60 %vbfdot3.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %.cast1) #3 61 ret <2 x float> %vbfdot3.i 62} 63 64define <4 x float> @test_vbfdotq_lane_f32(<4 x float> %r, <8 x bfloat> %a, <4 x bfloat> %b) { 65; CHECK-LABEL: test_vbfdotq_lane_f32: 66; CHECK: @ %bb.0: @ %entry 67; CHECK-NEXT: @ kill: def $d4 killed $d4 def $q2 68; CHECK-NEXT: vdot.bf16 q0, q1, d4[0] 69; CHECK-NEXT: bx lr 70entry: 71 %.cast = bitcast <4 x bfloat> %b to <2 x float> 72 %lane = shufflevector <2 x float> %.cast, <2 x float> undef, <4 x i32> zeroinitializer 73 %.cast1 = bitcast <4 x float> %lane to <8 x bfloat> 74 %vbfdot3.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %.cast1) #3 75 ret <4 x float> %vbfdot3.i 76} 77 78define <4 x float> @test_vbfmmlaq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) { 79; CHECK-LABEL: test_vbfmmlaq_f32: 80; CHECK: @ %bb.0: @ %entry 81; CHECK-NEXT: vmmla.bf16 q0, q1, q2 82; CHECK-NEXT: bx lr 83entry: 84 %vbfmmlaq_v3.i = call <4 x float> @llvm.arm.neon.bfmmla(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) 85 ret <4 x float> %vbfmmlaq_v3.i 86} 87 88define <4 x float> @test_vbfmlalbq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) { 89; CHECK-LABEL: test_vbfmlalbq_f32: 90; CHECK: @ %bb.0: @ %entry 91; CHECK-NEXT: vfmab.bf16 q0, q1, q2 92; CHECK-NEXT: bx lr 93entry: 94 %vbfmlalbq_v3.i = call <4 x float> @llvm.arm.neon.bfmlalb(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) 95 ret <4 x float> %vbfmlalbq_v3.i 96} 97 98define <4 x float> @test_vbfmlaltq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) { 99; CHECK-LABEL: test_vbfmlaltq_f32: 100; CHECK: @ %bb.0: @ %entry 101; CHECK-NEXT: vfmat.bf16 q0, q1, q2 102; CHECK-NEXT: bx lr 103entry: 104 %vbfmlaltq_v3.i = call <4 x float> @llvm.arm.neon.bfmlalt(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) 105 ret <4 x float> %vbfmlaltq_v3.i 106} 107 108define <4 x float> @test_vbfmlalbq_lane_f32(<4 x float> %r, <8 x bfloat> %a, <4 x bfloat> %b) { 109; CHECK-LABEL: test_vbfmlalbq_lane_f32: 110; CHECK: @ %bb.0: @ %entry 111; CHECK-NEXT: @ kill: def $d4 killed $d4 def $q2 112; CHECK-NEXT: vfmab.bf16 q0, q1, d4[0] 113; CHECK-NEXT: bx lr 114entry: 115 %vecinit35 = shufflevector <4 x bfloat> %b, <4 x bfloat> undef, <8 x i32> zeroinitializer 116 %vbfmlalbq_v3.i = call <4 x float> @llvm.arm.neon.bfmlalb(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %vecinit35) 117 ret <4 x float> %vbfmlalbq_v3.i 118} 119 120define <4 x float> @test_vbfmlalbq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) { 121; CHECK-LABEL: test_vbfmlalbq_laneq_f32: 122; CHECK: @ %bb.0: @ %entry 123; CHECK-NEXT: vfmab.bf16 q0, q1, d4[3] 124; CHECK-NEXT: bx lr 125entry: 126 %vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> 127 %vbfmlalbq_v3.i = call <4 x float> @llvm.arm.neon.bfmlalb(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %vecinit35) 128 ret <4 x float> %vbfmlalbq_v3.i 129} 130 131define <4 x float> @test_vbfmlaltq_lane_f32(<4 x float> %r, <8 x bfloat> %a, <4 x bfloat> %b) { 132; CHECK-LABEL: test_vbfmlaltq_lane_f32: 133; CHECK: @ %bb.0: @ %entry 134; CHECK-NEXT: @ kill: def $d4 killed $d4 def $q2 135; CHECK-NEXT: vfmat.bf16 q0, q1, d4[0] 136; CHECK-NEXT: bx lr 137entry: 138 %vecinit35 = shufflevector <4 x bfloat> %b, <4 x bfloat> undef, <8 x i32> zeroinitializer 139 %vbfmlaltq_v3.i = call <4 x float> @llvm.arm.neon.bfmlalt(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %vecinit35) 140 ret <4 x float> %vbfmlaltq_v3.i 141} 142 143define <4 x float> @test_vbfmlaltq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) { 144; CHECK-LABEL: test_vbfmlaltq_laneq_f32: 145; CHECK: @ %bb.0: @ %entry 146; CHECK-NEXT: vfmat.bf16 q0, q1, d4[3] 147; CHECK-NEXT: bx lr 148entry: 149 %vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3> 150 %vbfmlaltq_v3.i = call <4 x float> @llvm.arm.neon.bfmlalt(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %vecinit35) 151 ret <4 x float> %vbfmlaltq_v3.i 152} 153 154define <4 x float> @test_vbfmlaltq_laneq_f32_v2(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) { 155; CHECK-LABEL: test_vbfmlaltq_laneq_f32_v2: 156; CHECK: @ %bb.0: @ %entry 157; CHECK-NEXT: vdup.16 q8, d5[2] 158; CHECK-NEXT: vfmat.bf16 q0, q1, q8 159; CHECK-NEXT: bx lr 160entry: 161 %vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6> 162 %vbfmlalt1.i = call <4 x float> @llvm.arm.neon.bfmlalt(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %vecinit35) 163 ret <4 x float> %vbfmlalt1.i 164} 165 166declare <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float>, <4 x bfloat>, <4 x bfloat>) 167declare <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float>, <8 x bfloat>, <8 x bfloat>) 168declare <4 x float> @llvm.arm.neon.bfmmla(<4 x float>, <8 x bfloat>, <8 x bfloat>) 169declare <4 x float> @llvm.arm.neon.bfmlalb(<4 x float>, <8 x bfloat>, <8 x bfloat>) 170declare <4 x float> @llvm.arm.neon.bfmlalt(<4 x float>, <8 x bfloat>, <8 x bfloat>) 171