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Searched refs:v_add_f32_e64 (Results 1 – 25 of 44) sorted by relevance

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/external/llvm-project/llvm/test/MC/AMDGPU/
Dvop3-modifiers.s151 v_add_f32_e64 v0, -2, s0 label
154 v_add_f32_e64 v0, -16, s0 label
157 v_add_f32_e64 v0, -0.5, s0 label
160 v_add_f32_e64 v0, -1.0, s0 label
163 v_add_f32_e64 v0, -2.0, s0 label
166 v_add_f32_e64 v0, -4.0, s0 label
169 v_add_f32_e64 v0, 0x3e22f983, s0 label
172 v_add_f32_e64 v0, neg(0x3e22f983), s0 label
Dvop-err.s247 v_add_f32_e64 v0, s0, s1 label
250 v_add_f32_e64 v0, s0, flat_scratch_lo label
253 v_add_f32_e64 v0, flat_scratch_hi, s1 label
256 v_add_f32_e64 v0, flat_scratch_hi, m0 label
Dvop3-literal.s118 v_add_f32_e64 v1, neg(abs(0x123)), v3 label
122 v_add_f32_e64 v1, v3, neg(0x123) label
126 v_add_f32_e64 v1, neg(abs(0x12345678)), neg(0x12345678) label
Dlds_direct.s44 v_add_f32_e64 v0, src_lds_direct, v0 label
Dgfx9_err_pos.s122 v_add_f32_e64 v0, flat_scratch_hi, m0 label
Dvop3-errs.s6 v_add_f32_e64 v0, v1 label
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.AMDGPU.clamp.ll10 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}}
23 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, |[[ARG]]| clamp{{$}}
35 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, -[[ARG]] clamp{{$}}
47 ; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, -|[[ARG]]| clamp{{$}}
Dimm.ll131 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0, [[VAL]]{{$}}
141 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0.5, [[VAL]]{{$}}
151 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -0.5, [[VAL]]{{$}}
161 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1.0, [[VAL]]{{$}}
171 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1.0, [[VAL]]{{$}}
181 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, [[VAL]]{{$}}
191 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2.0, [[VAL]]{{$}}
201 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 4.0, [[VAL]]{{$}}
211 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -4.0, [[VAL]]{{$}}
243 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1, [[VAL]]{{$}}
[all …]
Dfmul-2-combine-multi-use.ll30 ; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], [[X:s[0-9]+]], s{{[0-9]+}}
45 ; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], |[[X:s[0-9]+]]|, |s{{[0-9]+}}|
Dcommute_modifiers.ll9 ; SI: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, |[[X]]|
54 ; SI: v_add_f32_e64 [[REG:v[0-9]+]], |[[X]]|, [[K]]
69 ; SI: v_add_f32_e64 [[REG:v[0-9]+]], [[X]], |[[Y]]|
Dfneg.ll51 ; XXX: We could use v_add_f32_e64 with the negate bit here instead.
Dcvt_flr_i32_f32.ll21 ; SI: v_add_f32_e64 [[TMP:v[0-9]+]], 1.0, s{{[0-9]+}}
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Domod.ll48 ; GCN: v_add_f32_e64 v{{[0-9]+}}, v0, 1.0 div:2{{$}}
57 ; GCN: v_add_f32_e64 v{{[0-9]+}}, v0, 1.0 mul:2{{$}}
66 ; GCN: v_add_f32_e64 v{{[0-9]+}}, v0, 1.0 mul:4{{$}}
86 ; GCN: v_add_f32_e64 v{{[0-9]+}}, v0, 1.0 mul:4{{$}}
97 ; GCN: v_add_f32_e64 v{{[0-9]+}}, v0, 1.0 clamp div:2{{$}}
110 ; GCN: v_add_f32_e64 [[ADD:v[0-9]+]], v0, 1.0 clamp{{$}}
133 ; GCN: v_add_f32_e64 v{{[0-9]+}}, v0, v0 clamp{{$}}
155 ; GCN: v_add_f32_e64 v{{[0-9]+}}, |[[X]]|, |[[X]]|{{$}}
167 ; GCN: v_add_f32_e64 v{{[0-9]+}}, |[[X]]|, [[X]]{{$}}
178 ; GCN: v_add_f32_e64 v{{[0-9]+}}, [[X]], |[[X]]|{{$}}
[all …]
Dxor3.ll142 ; GFX9-NEXT: v_add_f32_e64 v0, s2, 1.0
143 ; GFX9-NEXT: v_add_f32_e64 v1, s3, 2.0
151 ; GFX10-NEXT: v_add_f32_e64 v0, s2, 1.0
152 ; GFX10-NEXT: v_add_f32_e64 v1, s3, 2.0
153 ; GFX10-NEXT: v_add_f32_e64 v2, 0x40400000, s4
Dadd3.ll221 ; VI-NEXT: v_add_f32_e64 v0, s2, 1.0
222 ; VI-NEXT: v_add_f32_e64 v1, s3, 2.0
231 ; GFX9-NEXT: v_add_f32_e64 v0, s2, 1.0
232 ; GFX9-NEXT: v_add_f32_e64 v1, s3, 2.0
240 ; GFX10-NEXT: v_add_f32_e64 v0, s2, 1.0
241 ; GFX10-NEXT: v_add_f32_e64 v1, s3, 2.0
242 ; GFX10-NEXT: v_add_f32_e64 v2, 0x40400000, s4
Dimm.ll431 ; SI-NEXT: v_add_f32_e64 v0, s0, 0
442 ; VI-NEXT: v_add_f32_e64 v0, s0, 0
458 ; SI-NEXT: v_add_f32_e64 v0, s0, 0.5
469 ; VI-NEXT: v_add_f32_e64 v0, s0, 0.5
485 ; SI-NEXT: v_add_f32_e64 v0, s0, -0.5
496 ; VI-NEXT: v_add_f32_e64 v0, s0, -0.5
512 ; SI-NEXT: v_add_f32_e64 v0, s0, 1.0
523 ; VI-NEXT: v_add_f32_e64 v0, s0, 1.0
539 ; SI-NEXT: v_add_f32_e64 v0, s0, -1.0
550 ; VI-NEXT: v_add_f32_e64 v0, s0, -1.0
[all …]
Dfmul-2-combine-multi-use.ll20 ; GFX8_10: v_add_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, -1.0
21 ; GFX8_10: v_add_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, -1.0
24 ; GFX8_10: v_add_f32_e64 v{{[0-9]+}}, |v{{[0-9]+}}|, |v{{[0-9]+}}|
44 ; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], [[X:s[0-9]+]], s{{[0-9]+}}
60 ; GCN-DAG: v_add_f32_e64 [[MUL2:v[0-9]+]], |[[X:s[0-9]+]]|, |s{{[0-9]+}}|
Dclamp-modifier.ll8 ; GCN: v_add_f32_e64 v{{[0-9]+}}, [[A]], 1.0 clamp{{$}}
41 ; GCN: v_add_f32_e64 v{{[0-9]+}}, [[A]], 1.0 clamp{{$}}
89 ; GCN: v_add_f32_e64 [[ADD:v[0-9]+]], [[A]], 1.0 clamp{{$}}
107 ; SI: v_add_f32_e64 [[ADD:v[0-9]+]], [[CVT]], 1.0 clamp{{$}}
127 ; SI: v_add_f32_e64 [[ADD:v[0-9]+]], [[CVT]], 1.0 clamp{{$}}
143 ; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, v[[A]], 1.0 clamp{{$}}
144 ; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, v[[B]], 1.0 clamp{{$}}
Dcommute_modifiers.ll9 ; SI: v_add_f32_e64 [[REG:v[0-9]+]], |[[X]]|, 2.0
54 ; SI: v_add_f32_e64 [[REG:v[0-9]+]], |[[X]]|, [[K]]
69 ; SI: v_add_f32_e64 [[REG:v[0-9]+]], [[X]], |[[Y]]|
Dselect-fabs-fneg-extract.ll10 ; GCN: v_add_f32_e64 v{{[0-9]+}}, |[[SELECT]]|, [[Z]]
31 ; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, |[[SELECT]]|, [[Z]]
32 ; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, |[[X]]|, [[W]]
55 ; GCN-DAG: v_add_f32_e64 [[ADD:v[0-9]+]], |[[SELECT]]|, [[Z]]
81 ; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, |[[SELECT]]|, [[Z]]
82 ; GCN-DAG: v_add_f32_e64 v{{[0-9]+}}, |[[Y]]|, [[W]]
140 ; GCN: v_add_f32_e64 v{{[0-9]+}}, |[[SELECT]]|, [[X]]
207 ; GCN: v_add_f32_e64 v{{[0-9]+}}, |[[SELECT]]|, [[Y]]
226 ; GCN: v_add_f32_e64 v{{[0-9]+}}, |[[SELECT]]|, [[Y]]
Dstrict_fadd.f32.ll93 ; GCN-NEXT: v_add_f32_e64 v0, |v0|, v1
104 ; GCN-NEXT: v_add_f32_e64 v0, v0, |v1|
Dcvt_flr_i32_f32.ll21 ; SI: v_add_f32_e64 [[TMP:v[0-9]+]], s{{[0-9]+}}, 1.0
Dfabs.ll103 ; GCN: v_add_f32_e64 v{{[0-9]+}}, |s{{[0-9]+}}|, 1.0
/external/llvm/test/MC/AMDGPU/
Dvop3-errs.s4 v_add_f32_e64 v0, v1 label
Dvop3.s194 v_add_f32_e64 v1, v3, v5 label

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