Home
last modified time | relevance | path

Searched refs:vclz (Results 1 – 25 of 47) sorted by relevance

12

/external/llvm-project/llvm/test/MC/ARM/
Dneon-bitcount-encoding.s7 @ CHECK: vclz.i8 d16, d16 @ encoding: [0xa0,0x04,0xf0,0xf3]
8 vclz.i8 d16, d16
9 @ CHECK: vclz.i16 d16, d16 @ encoding: [0xa0,0x04,0xf4,0xf3]
10 vclz.i16 d16, d16
11 @ CHECK: vclz.i32 d16, d16 @ encoding: [0xa0,0x04,0xf8,0xf3]
12 vclz.i32 d16, d16
13 @ CHECK: vclz.i8 q8, q8 @ encoding: [0xe0,0x04,0xf0,0xf3]
14 vclz.i8 q8, q8
15 @ CHECK: vclz.i16 q8, q8 @ encoding: [0xe0,0x04,0xf4,0xf3]
16 vclz.i16 q8, q8
[all …]
Dneont2-bitcount-encoding.s11 vclz.i8 d16, d16
12 vclz.i16 d16, d16
13 vclz.i32 d16, d16
14 vclz.i8 q8, q8
15 vclz.i16 q8, q8
16 vclz.i32 q8, q8
18 @ CHECK: vclz.i8 d16, d16 @ encoding: [0xf0,0xff,0xa0,0x04]
19 @ CHECK: vclz.i16 d16, d16 @ encoding: [0xf4,0xff,0xa0,0x04]
20 @ CHECK: vclz.i32 d16, d16 @ encoding: [0xf8,0xff,0xa0,0x04]
21 @ CHECK: vclz.i8 q8, q8 @ encoding: [0xf0,0xff,0xe0,0x04]
[all …]
Dmve-integer.s234 # CHECK: vclz.i8 q0, q7 @ encoding: [0xb0,0xff,0xce,0x04]
235 vclz.i8 q0, q7
237 # CHECK: vclz.i16 q4, q7 @ encoding: [0xb4,0xff,0xce,0x84]
238 vclz.i16 q4, q7
240 # CHECK: vclz.i32 q7, q5 @ encoding: [0xb8,0xff,0xca,0xe4]
241 vclz.i32 q7, q5
/external/llvm/test/MC/ARM/
Dneon-bitcount-encoding.s7 @ CHECK: vclz.i8 d16, d16 @ encoding: [0xa0,0x04,0xf0,0xf3]
8 vclz.i8 d16, d16
9 @ CHECK: vclz.i16 d16, d16 @ encoding: [0xa0,0x04,0xf4,0xf3]
10 vclz.i16 d16, d16
11 @ CHECK: vclz.i32 d16, d16 @ encoding: [0xa0,0x04,0xf8,0xf3]
12 vclz.i32 d16, d16
13 @ CHECK: vclz.i8 q8, q8 @ encoding: [0xe0,0x04,0xf0,0xf3]
14 vclz.i8 q8, q8
15 @ CHECK: vclz.i16 q8, q8 @ encoding: [0xe0,0x04,0xf4,0xf3]
16 vclz.i16 q8, q8
[all …]
Dneont2-bitcount-encoding.s11 vclz.i8 d16, d16
12 vclz.i16 d16, d16
13 vclz.i32 d16, d16
14 vclz.i8 q8, q8
15 vclz.i16 q8, q8
16 vclz.i32 q8, q8
18 @ CHECK: vclz.i8 d16, d16 @ encoding: [0xf0,0xff,0xa0,0x04]
19 @ CHECK: vclz.i16 d16, d16 @ encoding: [0xf4,0xff,0xa0,0x04]
20 @ CHECK: vclz.i32 d16, d16 @ encoding: [0xf8,0xff,0xa0,0x04]
21 @ CHECK: vclz.i8 q8, q8 @ encoding: [0xf0,0xff,0xe0,0x04]
[all …]
/external/capstone/suite/MC/ARM/
Dneon-bitcount-encoding.s.cs4 0xa0,0x04,0xf0,0xf3 = vclz.i8 d16, d16
5 0xa0,0x04,0xf4,0xf3 = vclz.i16 d16, d16
6 0xa0,0x04,0xf8,0xf3 = vclz.i32 d16, d16
7 0xe0,0x04,0xf0,0xf3 = vclz.i8 q8, q8
8 0xe0,0x04,0xf4,0xf3 = vclz.i16 q8, q8
9 0xe0,0x04,0xf8,0xf3 = vclz.i32 q8, q8
Dneont2-bitcount-encoding.s.cs4 0xf0,0xff,0xa0,0x04 = vclz.i8 d16, d16
5 0xf4,0xff,0xa0,0x04 = vclz.i16 d16, d16
6 0xf8,0xff,0xa0,0x04 = vclz.i32 d16, d16
7 0xf0,0xff,0xe0,0x04 = vclz.i8 q8, q8
8 0xf4,0xff,0xe0,0x04 = vclz.i16 q8, q8
9 0xf8,0xff,0xe0,0x04 = vclz.i32 q8, q8
/external/llvm/test/CodeGen/ARM/
Dvcnt.ll2 ; NB: this tests vcnt, vclz, and vcls
25 ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
33 ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
41 ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
56 ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
64 ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
72 ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
87 ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
95 ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
103 ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
[all …]
Dpopcnt.ll99 ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
107 ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
115 ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
123 ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
131 ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
139 ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
Dcttz_vector.ll285 ; CHECK: vclz.i16 [[D1]], [[D1]]
300 ; CHECK: vclz.i16 [[Q1]], [[Q1]]
323 ; CHECK: vclz.i32 [[D1]], [[D1]]
338 ; CHECK: vclz.i32 [[Q1]], [[Q1]]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dvcnt.ll2 ; NB: this tests vcnt, vclz, and vcls
25 ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
33 ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
41 ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
56 ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
64 ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
72 ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
87 ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
95 ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
103 ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
[all …]
Dpopcnt.ll130 ; CHECK-NEXT: vclz.i8 d16, d16
142 ; CHECK-NEXT: vclz.i16 d16, d16
154 ; CHECK-NEXT: vclz.i32 d16, d16
166 ; CHECK-NEXT: vclz.i8 q8, q8
179 ; CHECK-NEXT: vclz.i16 q8, q8
192 ; CHECK-NEXT: vclz.i32 q8, q8
Dcttz_vector.ll51 ; CHECK-NEXT: vclz.i32 d16, d16
143 ; CHECK-NEXT: vclz.i32 d16, d16
309 ; CHECK-NEXT: vclz.i32 d16, d16
330 ; CHECK-NEXT: vclz.i16 d16, d16
397 ; CHECK-NEXT: vclz.i32 d16, d16
415 ; CHECK-NEXT: vclz.i16 d16, d16
432 ; CHECK-NEXT: vclz.i16 q8, q8
463 ; CHECK-NEXT: vclz.i32 d16, d16
480 ; CHECK-NEXT: vclz.i32 q8, q8
/external/llvm/test/CodeGen/AArch64/
Darm64-vclz.ll7 %vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
8 ret <8 x i8> %vclz.i
15 %vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
16 ret <8 x i8> %vclz.i
67 %vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
68 ret <16 x i8> %vclz.i
75 %vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
76 ret <16 x i8> %vclz.i
/external/llvm-project/llvm/test/Bitcode/
Darm32_neon_vcnt_upgrade.ll3 ; Tests vclz and vcnt
8 %tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1)
21 declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone
/external/llvm/test/Bitcode/
Darm32_neon_vcnt_upgrade.ll3 ; Tests vclz and vcnt
8 %tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1)
21 declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone
/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-vclz.ll9 %vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
10 ret <8 x i8> %vclz.i
18 %vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
19 ret <8 x i8> %vclz.i
77 %vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
78 ret <16 x i8> %vclz.i
86 %vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
87 ret <16 x i8> %vclz.i
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dmve-ctlz.ll43 ; CHECK-NEXT: vclz.i32 q0, q0
53 ; CHECK-NEXT: vclz.i16 q0, q0
63 ; CHECK-NEXT: vclz.i8 q0, q0
109 ; CHECK-NEXT: vclz.i32 q0, q0
119 ; CHECK-NEXT: vclz.i16 q0, q0
129 ; CHECK-NEXT: vclz.i8 q0, q0
Dmve-cttz.ll49 ; CHECK-NEXT: vclz.i32 q0, q0
61 ; CHECK-NEXT: vclz.i16 q0, q0
73 ; CHECK-NEXT: vclz.i8 q0, q0
125 ; CHECK-NEXT: vclz.i32 q0, q0
137 ; CHECK-NEXT: vclz.i16 q0, q0
149 ; CHECK-NEXT: vclz.i8 q0, q0
/external/arm-neon-tests/
DMakefile.gcc59 vqshlu_n vclz vcls vcnt vqshrn_n vpmax vpmin vqshrun_n \
Dref_vclz.c34 #define INSN_NAME vclz
DMakefile53 vqshlu_n vclz vcls vcnt vqshrn_n vpmax vpmin vqshrun_n \
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dmve-integer.txt319 # CHECK: vclz.i8 q0, q7 @ encoding: [0xb0,0xff,0xce,0x04]
323 # CHECK: vclz.i16 q4, q7 @ encoding: [0xb4,0xff,0xce,0x84]
327 # CHECK: vclz.i32 q7, q5 @ encoding: [0xb8,0xff,0xca,0xe4]
/external/llvm-project/llvm/test/tools/llvm-mca/ARM/
Dcortex-a57-neon-instructions.s123 vclz.i8 d16, d16
124 vclz.i16 d16, d16
125 vclz.i32 d16, d16
126 vclz.i8 q8, q8
127 vclz.i16 q8, q8
128 vclz.i32 q8, q8
1239 # CHECK-NEXT: 1 3 0.50 vclz.i8 d16, d16
1240 # CHECK-NEXT: 1 3 0.50 vclz.i16 d16, d16
1241 # CHECK-NEXT: 1 3 0.50 vclz.i32 d16, d16
1242 # CHECK-NEXT: 1 3 0.50 vclz.i8 q8, q8
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dneont2.txt253 # CHECK: vclz.i8 d16, d16
255 # CHECK: vclz.i16 d16, d16
257 # CHECK: vclz.i32 d16, d16
259 # CHECK: vclz.i8 q8, q8
261 # CHECK: vclz.i16 q8, q8
263 # CHECK: vclz.i32 q8, q8

12