1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s 3 4define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_0_t(<2 x i64> %src){ 5; CHECK-LABEL: ctlz_2i64_0_t: 6; CHECK: @ %bb.0: @ %entry 7; CHECK-NEXT: vmov r0, s3 8; CHECK-NEXT: cmp r0, #0 9; CHECK-NEXT: cset r1, ne 10; CHECK-NEXT: lsls r1, r1, #31 11; CHECK-NEXT: vmov r1, s2 12; CHECK-NEXT: clz r1, r1 13; CHECK-NEXT: add.w r1, r1, #32 14; CHECK-NEXT: it ne 15; CHECK-NEXT: clzne r1, r0 16; CHECK-NEXT: vmov r0, s1 17; CHECK-NEXT: vmov s6, r1 18; CHECK-NEXT: cmp r0, #0 19; CHECK-NEXT: cset r1, ne 20; CHECK-NEXT: lsls r1, r1, #31 21; CHECK-NEXT: vmov r1, s0 22; CHECK-NEXT: clz r1, r1 23; CHECK-NEXT: add.w r1, r1, #32 24; CHECK-NEXT: it ne 25; CHECK-NEXT: clzne r1, r0 26; CHECK-NEXT: vmov s4, r1 27; CHECK-NEXT: vldr s5, .LCPI0_0 28; CHECK-NEXT: vmov.f32 s7, s5 29; CHECK-NEXT: vmov q0, q1 30; CHECK-NEXT: bx lr 31; CHECK-NEXT: .p2align 2 32; CHECK-NEXT: @ %bb.1: 33; CHECK-NEXT: .LCPI0_0: 34; CHECK-NEXT: .long 0x00000000 @ float 0 35entry: 36 %0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 0) 37 ret <2 x i64> %0 38} 39 40define arm_aapcs_vfpcc <4 x i32> @ctlz_4i32_0_t(<4 x i32> %src){ 41; CHECK-LABEL: ctlz_4i32_0_t: 42; CHECK: @ %bb.0: @ %entry 43; CHECK-NEXT: vclz.i32 q0, q0 44; CHECK-NEXT: bx lr 45entry: 46 %0 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %src, i1 0) 47 ret <4 x i32> %0 48} 49 50define arm_aapcs_vfpcc <8 x i16> @ctlz_8i16_0_t(<8 x i16> %src){ 51; CHECK-LABEL: ctlz_8i16_0_t: 52; CHECK: @ %bb.0: @ %entry 53; CHECK-NEXT: vclz.i16 q0, q0 54; CHECK-NEXT: bx lr 55entry: 56 %0 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %src, i1 0) 57 ret <8 x i16> %0 58} 59 60define arm_aapcs_vfpcc <16 x i8> @ctlz_16i8_0_t(<16 x i8> %src){ 61; CHECK-LABEL: ctlz_16i8_0_t: 62; CHECK: @ %bb.0: @ %entry 63; CHECK-NEXT: vclz.i8 q0, q0 64; CHECK-NEXT: bx lr 65entry: 66 %0 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %src, i1 0) 67 ret <16 x i8> %0 68} 69 70define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_1_t(<2 x i64> %src){ 71; CHECK-LABEL: ctlz_2i64_1_t: 72; CHECK: @ %bb.0: @ %entry 73; CHECK-NEXT: vmov r0, s3 74; CHECK-NEXT: cmp r0, #0 75; CHECK-NEXT: cset r1, ne 76; CHECK-NEXT: lsls r1, r1, #31 77; CHECK-NEXT: vmov r1, s2 78; CHECK-NEXT: clz r1, r1 79; CHECK-NEXT: add.w r1, r1, #32 80; CHECK-NEXT: it ne 81; CHECK-NEXT: clzne r1, r0 82; CHECK-NEXT: vmov r0, s1 83; CHECK-NEXT: vmov s6, r1 84; CHECK-NEXT: cmp r0, #0 85; CHECK-NEXT: cset r1, ne 86; CHECK-NEXT: lsls r1, r1, #31 87; CHECK-NEXT: vmov r1, s0 88; CHECK-NEXT: clz r1, r1 89; CHECK-NEXT: add.w r1, r1, #32 90; CHECK-NEXT: it ne 91; CHECK-NEXT: clzne r1, r0 92; CHECK-NEXT: vmov s4, r1 93; CHECK-NEXT: vldr s5, .LCPI4_0 94; CHECK-NEXT: vmov.f32 s7, s5 95; CHECK-NEXT: vmov q0, q1 96; CHECK-NEXT: bx lr 97; CHECK-NEXT: .p2align 2 98; CHECK-NEXT: @ %bb.1: 99; CHECK-NEXT: .LCPI4_0: 100; CHECK-NEXT: .long 0x00000000 @ float 0 101entry: 102 %0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 1) 103 ret <2 x i64> %0 104} 105 106define arm_aapcs_vfpcc <4 x i32> @ctlz_4i32_1_t(<4 x i32> %src){ 107; CHECK-LABEL: ctlz_4i32_1_t: 108; CHECK: @ %bb.0: @ %entry 109; CHECK-NEXT: vclz.i32 q0, q0 110; CHECK-NEXT: bx lr 111entry: 112 %0 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %src, i1 1) 113 ret <4 x i32> %0 114} 115 116define arm_aapcs_vfpcc <8 x i16> @ctlz_8i16_1_t(<8 x i16> %src){ 117; CHECK-LABEL: ctlz_8i16_1_t: 118; CHECK: @ %bb.0: @ %entry 119; CHECK-NEXT: vclz.i16 q0, q0 120; CHECK-NEXT: bx lr 121entry: 122 %0 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %src, i1 1) 123 ret <8 x i16> %0 124} 125 126define arm_aapcs_vfpcc <16 x i8> @ctlz_16i8_1_t(<16 x i8> %src){ 127; CHECK-LABEL: ctlz_16i8_1_t: 128; CHECK: @ %bb.0: @ %entry 129; CHECK-NEXT: vclz.i8 q0, q0 130; CHECK-NEXT: bx lr 131entry: 132 %0 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %src, i1 1) 133 ret <16 x i8> %0 134} 135 136 137declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) 138declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) 139declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) 140declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) 141