Searched refs:vform (Results 1 – 6 of 6) sorted by relevance
| /external/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 170 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1() argument
171 dst.ClearForWrite(vform); in ld1()
172 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld1()
173 LoadLane(dst, vform, i, addr); in ld1()
174 addr += LaneSizeInBytesFromFormat(vform); in ld1()
179 void Simulator::ld1(VectorFormat vform, in ld1() argument
183 LoadLane(dst, vform, index, addr); in ld1()
187 void Simulator::ld1r(VectorFormat vform, in ld1r() argument
193 dst.ClearForWrite(vform); in ld1r()
194 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld1r()
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| D | simulator-aarch64.h | 412 void SetActive(VectorFormat vform, int lane_index, bool value) { in SetActive() argument
413 int psize = LaneSizeInBytesFromFormat(vform); in SetActive()
421 bool IsActive(VectorFormat vform, int lane_index) const { in IsActive() argument
422 int psize = LaneSizeInBytesFromFormat(vform); in IsActive()
512 int64_t Int(VectorFormat vform, int index) const { in Int() argument
513 if (IsSVEFormat(vform)) register_.NotifyAccessAsZ(); in Int()
515 switch (LaneSizeInBitsFromFormat(vform)) { in Int()
535 uint64_t Uint(VectorFormat vform, int index) const { in Uint() argument
536 if (IsSVEFormat(vform)) register_.NotifyAccessAsZ(); in Uint()
538 switch (LaneSizeInBitsFromFormat(vform)) { in Uint()
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| D | instructions-aarch64.cc | 1008 VectorFormat VectorFormatHalfWidth(VectorFormat vform) { in VectorFormatHalfWidth() argument
1009 switch (vform) { in VectorFormatHalfWidth()
1036 VectorFormat VectorFormatDoubleWidth(VectorFormat vform) { in VectorFormatDoubleWidth() argument
1037 VIXL_ASSERT(vform == kFormat8B || vform == kFormat4H || vform == kFormat2S || in VectorFormatDoubleWidth()
1038 vform == kFormatB || vform == kFormatH || vform == kFormatS); in VectorFormatDoubleWidth()
1039 switch (vform) { in VectorFormatDoubleWidth()
1059 VectorFormat VectorFormatFillQ(VectorFormat vform) { in VectorFormatFillQ() argument
1060 switch (vform) { in VectorFormatFillQ()
1083 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform) { in VectorFormatHalfWidthDoubleLanes() argument
1084 switch (vform) { in VectorFormatHalfWidthDoubleLanes()
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| D | simulator-aarch64.cc | 374 void Simulator::ExtractFromSimVRegister(VectorFormat vform, in ExtractFromSimVRegister() argument
380 vform, in ExtractFromSimVRegister()
674 VectorFormat vform) { in GetPrintRegisterFormat() argument
675 switch (vform) { in GetPrintRegisterFormat()
718 VectorFormat vform) { in GetPrintRegisterFormatFP() argument
719 switch (vform) { in GetPrintRegisterFormatFP()
4087 VectorFormat vform; in VisitFPDataProcessing1Source() local
4092 vform = kFormatD; in VisitFPDataProcessing1Source()
4095 vform = kFormatS; in VisitFPDataProcessing1Source()
4098 vform = kFormatH; in VisitFPDataProcessing1Source()
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| D | instructions-aarch64.h | 682 VectorFormat VectorFormatHalfWidth(VectorFormat vform);
683 VectorFormat VectorFormatDoubleWidth(VectorFormat vform);
684 VectorFormat VectorFormatDoubleLanes(VectorFormat vform);
685 VectorFormat VectorFormatHalfLanes(VectorFormat vform);
687 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform);
688 VectorFormat VectorFormatFillQ(VectorFormat vform);
689 VectorFormat ScalarFormatFromFormat(VectorFormat vform);
693 unsigned RegisterSizeInBitsFromFormat(VectorFormat vform);
694 unsigned RegisterSizeInBytesFromFormat(VectorFormat vform);
695 bool IsSVEFormat(VectorFormat vform);
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| /external/marisa-trie/bindings/perl/ |
| D | marisa-swig_wrap.cxx | 1432 #ifdef vform
1433 #undef vform
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