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/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dcombine-amdgpu-cvt-f32-ubyte.mir9 liveins: $vgpr0
12 ; CHECK: liveins: $vgpr0
13 ; CHECK: %arg:_(s32) = COPY $vgpr0
15 ; CHECK: $vgpr0 = COPY %result(s32)
16 %arg:_(s32) = COPY $vgpr0
20 $vgpr0 = COPY %result
28 liveins: $vgpr0
31 ; CHECK: liveins: $vgpr0
32 ; CHECK: %arg:_(s32) = COPY $vgpr0
34 ; CHECK: $vgpr0 = COPY %result(s32)
[all …]
Dinst-select-load-local.mir17 liveins: $vgpr0
20 ; GFX7: liveins: $vgpr0
21 ; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
24 ; GFX7: $vgpr0 = COPY [[DS_READ_B32_]]
26 ; GFX9: liveins: $vgpr0
27 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
29 ; GFX9: $vgpr0 = COPY [[DS_READ_B32_gfx9_]]
31 ; GFX6: liveins: $vgpr0
32 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
35 ; GFX6: $vgpr0 = COPY [[DS_READ_B32_]]
[all …]
Dinst-select-load-private.mir17 liveins: $vgpr0
20 ; GFX6: liveins: $vgpr0
21 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
23 ; GFX6: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
25 ; GFX9: liveins: $vgpr0
26 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
28 ; GFX9: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_OFFEN]]
29 %0:vgpr(p5) = COPY $vgpr0
31 $vgpr0 = COPY %1
47 liveins: $vgpr0
[all …]
Dinst-select-load-atomic-local.mir15 liveins: $vgpr0
18 ; GFX6: liveins: $vgpr0
19 ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
22 ; GFX6: $vgpr0 = COPY [[DS_READ_B32_]]
24 ; GFX7: liveins: $vgpr0
25 ; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
28 ; GFX7: $vgpr0 = COPY [[DS_READ_B32_]]
30 ; GFX9: liveins: $vgpr0
31 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
33 ; GFX9: $vgpr0 = COPY [[DS_READ_B32_gfx9_]]
[all …]
Dcombine-itofp.mir9 liveins: $vgpr0
12 ; CHECK: liveins: $vgpr0
13 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
17 ; CHECK: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
18 %0:_(s32) = COPY $vgpr0
22 $vgpr0 = COPY %3
30 liveins: $vgpr0
33 ; CHECK: liveins: $vgpr0
34 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
38 ; CHECK: $vgpr0 = COPY [[UITOFP]](s32)
[all …]
Dinst-select-load-local-128.mir14 liveins: $vgpr0
17 ; GFX7: liveins: $vgpr0
18 ; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
23 ; GFX9: liveins: $vgpr0
24 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
27 %0:vgpr(p3) = COPY $vgpr0
42 liveins: $vgpr0
45 ; GFX7: liveins: $vgpr0
46 ; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
51 ; GFX9: liveins: $vgpr0
[all …]
Dinst-select-fptosi.mir12 liveins: $vgpr0
15 ; GCN: liveins: $vgpr0
16 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
18 ; GCN: $vgpr0 = COPY %1
19 %0:vgpr(s32) = COPY $vgpr0
21 $vgpr0 = COPY %1
38 ; GCN: $vgpr0 = COPY %1
41 $vgpr0 = COPY %1
52 liveins: $vgpr0
55 ; GCN: liveins: $vgpr0
[all …]
Dlegalize-extract.mir13 ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
16 $vgpr0 = COPY %1
27 ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
30 $vgpr0 = COPY %1
42 ; CHECK: $vgpr0 = COPY [[TRUNC]](s32)
47 $vgpr0 = COPY %3
59 ; CHECK: $vgpr0 = COPY [[TRUNC]](s32)
64 $vgpr0 = COPY %3
77 ; CHECK: $vgpr0 = COPY [[EXTRACT]](s32)
81 $vgpr0 = COPY %2
[all …]
Dinst-select-shuffle-vector.v2s16.mir12 liveins: $vgpr0, $vgpr1
15 ; GFX9: liveins: $vgpr0, $vgpr1
17 ; GFX9: $vgpr0 = COPY [[DEF]]
18 %0:vgpr(<2 x s16>) = COPY $vgpr0
21 $vgpr0 = COPY %2
33 liveins: $vgpr0, $vgpr1
36 ; GFX9: liveins: $vgpr0, $vgpr1
37 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
38 ; GFX9: $vgpr0 = COPY [[COPY]]
39 %0:vgpr(<2 x s16>) = COPY $vgpr0
[all …]
Dlegalize-sextload-private.mir9 liveins: $vgpr0
12 ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
14 ; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
15 %0:_(p5) = COPY $vgpr0
18 $vgpr0 = COPY %1
24 liveins: $vgpr0
27 ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
29 ; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
30 %0:_(p5) = COPY $vgpr0
32 $vgpr0 = COPY %1
[all …]
Dlegalize-sextload-local.mir8 liveins: $vgpr0
11 ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
13 ; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
14 %0:_(p3) = COPY $vgpr0
16 $vgpr0 = COPY %1
22 liveins: $vgpr0
25 ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
27 ; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
28 %0:_(p3) = COPY $vgpr0
30 $vgpr0 = COPY %1
[all …]
Dlegalize-zextload-private.mir9 liveins: $vgpr0
12 ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
14 ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
15 %0:_(p5) = COPY $vgpr0
17 $vgpr0 = COPY %1
23 liveins: $vgpr0
26 ; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
28 ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
29 %0:_(p5) = COPY $vgpr0
31 $vgpr0 = COPY %1
[all …]
Dlegalize-zextload-local.mir8 liveins: $vgpr0
11 ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
13 ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
14 %0:_(p3) = COPY $vgpr0
16 $vgpr0 = COPY %1
22 liveins: $vgpr0
25 ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
27 ; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
28 %0:_(p3) = COPY $vgpr0
30 $vgpr0 = COPY %1
[all …]
Dinst-select-uitofp.mir13 liveins: $vgpr0
16 ; WAVE64: liveins: $vgpr0
17 ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
19 ; WAVE64: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
21 ; WAVE32: liveins: $vgpr0
22 ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
24 ; WAVE32: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
25 %0:vgpr(s32) = COPY $vgpr0
27 $vgpr0 = COPY %1
44 ; WAVE64: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
[all …]
Dinst-select-atomicrmw-fadd-local.mir17 liveins: $vgpr0, $vgpr1
20 ; GFX8: liveins: $vgpr0, $vgpr1
21 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
25 ; GFX8: $vgpr0 = COPY [[DS_ADD_RTN_F32_]]
27 ; GFX9: liveins: $vgpr0, $vgpr1
28 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
31 ; GFX9: $vgpr0 = COPY [[DS_ADD_RTN_F32_gfx9_]]
33 ; GFX6: liveins: $vgpr0, $vgpr1
34 ; GFX6: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
38 ; GFX6: $vgpr0 = COPY [[ATOMICRMW_FADD]](s32)
[all …]
Dinst-select-atomicrmw-fadd-region.mir17 liveins: $vgpr0, $vgpr1
20 ; GFX8: liveins: $vgpr0, $vgpr1
21 ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
25 ; GFX8: $vgpr0 = COPY [[DS_ADD_RTN_F32_]]
27 ; GFX9: liveins: $vgpr0, $vgpr1
28 ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
31 ; GFX9: $vgpr0 = COPY [[DS_ADD_RTN_F32_]]
33 ; GFX6: liveins: $vgpr0, $vgpr1
34 ; GFX6: [[COPY:%[0-9]+]]:vgpr(p2) = COPY $vgpr0
38 ; GFX6: $vgpr0 = COPY [[ATOMICRMW_FADD]](s32)
[all …]
Dinst-select-amdgcn.fmed3.mir12 liveins: $vgpr0, $vgpr1, $vgpr2
15 ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
16 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
21 %0:vgpr(s32) = COPY $vgpr0
36 liveins: $sgpr0, $vgpr0, $vgpr1
39 ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
41 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
46 %1:vgpr(s32) = COPY $vgpr0
60 liveins: $sgpr0, $vgpr0, $vgpr1
63 ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dhard-clauses.mir42 liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr0
44 ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr0
45 … $vgpr64, implicit-def $vgpr64_lo16, implicit-def $vgpr64_hi16, implicit $vgpr0, implicit $sgpr0_s…
47 …; CHECK: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, 0, 0, 0,…
48 …; CHECK: $vgpr2 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 8, 0, 0, 0, 0, 0,…
49 …; CHECK: $vgpr3 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 12, 0, 0, 0, 0, 0…
50 …; CHECK: $vgpr4 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 16, 0, 0, 0, 0, 0…
51 …; CHECK: $vgpr5 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 20, 0, 0, 0, 0, 0…
52 …; CHECK: $vgpr6 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 24, 0, 0, 0, 0, 0…
53 …; CHECK: $vgpr7 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 28, 0, 0, 0, 0, 0…
[all …]
Dvmem-vcc-hazard.mir14 $vgpr0 = IMPLICIT_DEF
15 $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
18 …$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, impl…
31 $vgpr0 = IMPLICIT_DEF
32 $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
36 …$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, impl…
48 $vgpr0 = IMPLICIT_DEF
49 $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
57 …$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, impl…
69 $vgpr0 = IMPLICIT_DEF
[all …]
Doptimize-if-exec-masking.mir135 - { reg: '$vgpr0' }
138 liveins: $vgpr0
141 $vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec
142 $vgpr0 = V_MOV_B32_e32 4, implicit $exec
154 $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, implicit $exec
157 liveins: $vgpr0, $sgpr0_sgpr1
162 …BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, implicit $…
173 - { reg: '$vgpr0' }
176 liveins: $vgpr0
179 $vcc = V_CMP_EQ_I32_e64 0, killed $vgpr0, implicit $exec
[all …]
Dgws-hazards.mir13 liveins: $vgpr0
15 ; GFX9: liveins: $vgpr0
18 ; GFX9: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
20 ; VI: liveins: $vgpr0
23 ; VI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
25 ; CI: liveins: $vgpr0
27 ; CI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
29 ; SI: liveins: $vgpr0
31 ; SI: DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
33 DS_GWS_INIT $vgpr0, 0, implicit $m0, implicit $exec
[all …]
Dsmem-war-hazard.mir11 liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
13 $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
25 liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1
28 $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
41 liveins: $sgpr0, $sgpr1, $sgpr4, $vgpr0, $vgpr1
45 $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
58 liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1
62 $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
75 liveins: $sgpr0, $sgpr1, $sgpr6, $sgpr7, $vgpr0, $vgpr1
78 $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec
[all …]
Dfold-reload-into-exec.mir13 ; CHECK: liveins: $vgpr0
17 ; CHECK: $vgpr0 = V_WRITELANE_B32 killed $sgpr0, 0, undef $vgpr0
18 ; CHECK: $sgpr0 = V_READLANE_B32 $vgpr0, 0
20 ; CHECK: $sgpr0 = V_READLANE_B32 killed $vgpr0, 0
37 ; CHECK: liveins: $vgpr0
41 ; CHECK: $vgpr0 = V_WRITELANE_B32 killed $sgpr0, 0, undef $vgpr0
42 ; CHECK: $sgpr0 = V_READLANE_B32 $vgpr0, 0
44 ; CHECK: $sgpr0 = V_READLANE_B32 killed $vgpr0, 0
61 ; CHECK: liveins: $vgpr0
65 …; CHECK: $vgpr0 = V_WRITELANE_B32 killed $sgpr0, 0, undef $vgpr0, implicit-def $sgpr0_sgpr1, impli…
[all …]
Dvmem-to-salu-hazard.mir13 $vgpr0 = IMPLICIT_DEF
14 …$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, impli…
27 $vgpr0 = IMPLICIT_DEF
29 …BUFFER_STORE_DWORD_OFFEN_exact killed renamable $vgpr0, renamable $vgpr1, renamable $sgpr0_sgpr1_s…
47 $vgpr0 = IMPLICIT_DEF
48 …$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, impli…
65 $vgpr0 = IMPLICIT_DEF
66 …$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, impli…
80 $vgpr0 = IMPLICIT_DEF
81 …$vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, impli…
[all …]
Dmai-hazards.mir11 $vgpr0 = V_MOV_B32_e32 1, implicit $exec
13 …$agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_a…
24 $vgpr0 = V_MOV_B32_e32 1, implicit $exec
25 $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
35 …$agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_a…
36 …$agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_a…
47 …$agpr1_agpr2_agpr3_agpr4 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_a…
48 …$agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_a…
59 …gpr12_agpr13_agpr14_agpr15 = V_MFMA_F32_16X16X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agp…
60 …$agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_a…
[all …]

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