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Searched refs:vmovn (Results 1 – 25 of 89) sorted by relevance

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/external/libvpx/libvpx/vpx_dsp/arm/
Didct_neon.asm23 vmovn.i32 $dst0, q0
24 vmovn.i32 $dst1, q1
25 vmovn.i32 $dst2, q2
26 vmovn.i32 $dst3, q3
38 vmovn.i32 $dst0, q0
39 vmovn.i32 $dst1, q2
40 vmovn.i32 $dst2, q1
41 vmovn.i32 $dst3, q3
/external/libvpx/config/arm-neon/vpx_dsp/arm/
Didct_neon.asm.S25 vmovn.i32 \dst0, q0
26 vmovn.i32 \dst1, q1
27 vmovn.i32 \dst2, q2
28 vmovn.i32 \dst3, q3
39 vmovn.i32 \dst0, q0
40 vmovn.i32 \dst1, q2
41 vmovn.i32 \dst2, q1
42 vmovn.i32 \dst3, q3
/external/llvm/test/CodeGen/ARM/
Dneon_div.ll6 ;CHECK: vmovn.i32
8 ;CHECK: vmovn.i32
9 ;CHECK: vmovn.i16
19 ;CHECK: vmovn.i32
22 ;CHECK: vmovn.i32
33 ;CHECK: vmovn.i32
44 ;CHECK: vmovn.i32
Dvcvt-cost.ll40 ; CHECK: vmovn.i32
41 ; CHECK: vmovn.i32
42 ; CHECK: vmovn.i16
88 ; CHECK: vmovn.i32
89 ; CHECK: vmovn.i32
90 ; CHECK: vmovn.i32
91 ; CHECK: vmovn.i32
92 ; CHECK: vmovn.i16
93 ; CHECK: vmovn.i16
Dbig-endian-neon-trunc-store.ll5 ; CHECK: vmovn.i64 [[REG:d[0-9]+]]
17 ; CHECK: vmovn.i32 [[REG:d[0-9]+]]
Dvshrn.ll33 ; CHECK: vmovn.i16
43 ; CHECK: vmovn.i32
53 ; CHECK: vmovn.i64
Dvector-extend-narrow.ll45 ; CHECK: vmovn.i32
60 ; CHECK: vmovn
Dsetcc-type-mismatch.ll6 ; CHECK: vmovn.i32 {{d[0-9]+}}, [[CMP128]]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dneon_div.ll13 ; CHECK: vmovn.i32
15 ; CHECK: vmovn.i32
16 ; CHECK: vmovn.i16
28 ; CHECK: vmovn.i32
31 ; CHECK: vmovn.i32
44 ; CHECK: vmovn.i32
57 ; CHECK: vmovn.i32
Dvcvt-cost.ll40 ; CHECK: vmovn.i32
41 ; CHECK: vmovn.i32
42 ; CHECK: vmovn.i16
88 ; CHECK: vmovn.i32
89 ; CHECK: vmovn.i32
90 ; CHECK: vmovn.i32
91 ; CHECK: vmovn.i32
92 ; CHECK: vmovn.i16
93 ; CHECK: vmovn.i16
Dbig-endian-neon-trunc-store.ll5 ; CHECK: vmovn.i64 [[REG:d[0-9]+]]
17 ; CHECK: vmovn.i32 [[REG:d[0-9]+]]
DlowerMUL-newload.ll12 ; CHECK-NEXT: vmovn.i32 d19, q10
19 ; CHECK-NEXT: vmovn.i32 d16, q11
23 ; CHECK-NEXT: vmovn.i32 d16, q11
83 ; CHECK-NEXT: vmovn.i32 d19, q10
90 ; CHECK-NEXT: vmovn.i32 d16, q11
95 ; CHECK-NEXT: vmovn.i32 d16, q8
Dneon-vmovn.ll5 ; This is the same as Thumb2/mve-vmovn.ll, testing the same patterns for neon
6 ; under both both LE and BE. The vmovn instruction is very different between
8 ; vmovn.
14 ; CHECK-NEXT: vmovn.i32 d17, q1
15 ; CHECK-NEXT: vmovn.i32 d16, q0
24 ; CHECKBE-NEXT: vmovn.i32 d17, q8
25 ; CHECKBE-NEXT: vmovn.i32 d16, q9
38 ; CHECK-NEXT: vmovn.i32 d1, q0
39 ; CHECK-NEXT: vmovn.i32 d0, q1
47 ; CHECKBE-NEXT: vmovn.i32 d17, q8
[all …]
Dvshrn.ll33 ; CHECK: vmovn.i16
43 ; CHECK: vmovn.i32
53 ; CHECK: vmovn.i64
Dvector-extend-narrow.ll45 ; CHECK: vmovn.i32
60 ; CHECK: vmovn
/external/libhevc/common/arm/
Dihevc_intra_pred_luma_planar.s220 vmovn.i16 d12, q6 @(1)
237 vmovn.i16 d30, q15 @(2)
254 vmovn.i16 d28, q14 @(3)
270 vmovn.i16 d10, q5 @(4)
287 vmovn.i16 d16, q8 @(5)
304 vmovn.i16 d18, q9 @(6)
351 vmovn.i16 d26, q13 @(7)
354 vmovn.i16 d24, q12 @(8)
389 vmovn.i16 d12, q6 @(1)
407 vmovn.i16 d30, q15 @(2)
[all …]
Dihevc_intra_pred_chroma_planar.s222 vmovn.i16 d12, q6
224 vmovn.i16 d13,q14
251 vmovn.i16 d26, q13
253 vmovn.i16 d27,q12
275 vmovn.i16 d22, q11
279 vmovn.i16 d23,q10
290 vmovn.i16 d20, q6
291 vmovn.i16 d21,q14
347 @ vmovn.i16 d12, q6
/external/llvm/test/MC/ARM/
Dneont2-mov-encoding.s76 vmovn.i16 d16, q8
77 vmovn.i32 d16, q8
78 vmovn.i64 d16, q8
95 @ CHECK: vmovn.i16 d16, q8 @ encoding: [0xf2,0xff,0x20,0x02]
96 @ CHECK: vmovn.i32 d16, q8 @ encoding: [0xf6,0xff,0x20,0x02]
97 @ CHECK: vmovn.i64 d16, q8 @ encoding: [0xfa,0xff,0x20,0x02]
Dneon-mov-encoding.s82 vmovn.i16 d16, q8
83 vmovn.i32 d16, q8
84 vmovn.i64 d16, q8
95 @ CHECK: vmovn.i16 d16, q8 @ encoding: [0x20,0x02,0xf2,0xf3]
96 @ CHECK: vmovn.i32 d16, q8 @ encoding: [0x20,0x02,0xf6,0xf3]
97 @ CHECK: vmovn.i64 d16, q8 @ encoding: [0x20,0x02,0xfa,0xf3]
/external/llvm-project/llvm/test/MC/ARM/
Dneont2-mov-encoding.s76 vmovn.i16 d16, q8
77 vmovn.i32 d16, q8
78 vmovn.i64 d16, q8
95 @ CHECK: vmovn.i16 d16, q8 @ encoding: [0xf2,0xff,0x20,0x02]
96 @ CHECK: vmovn.i32 d16, q8 @ encoding: [0xf6,0xff,0x20,0x02]
97 @ CHECK: vmovn.i64 d16, q8 @ encoding: [0xfa,0xff,0x20,0x02]
Dneon-mov-encoding.s82 vmovn.i16 d16, q8
83 vmovn.i32 d16, q8
84 vmovn.i64 d16, q8
95 @ CHECK: vmovn.i16 d16, q8 @ encoding: [0x20,0x02,0xf2,0xf3]
96 @ CHECK: vmovn.i32 d16, q8 @ encoding: [0x20,0x02,0xf6,0xf3]
97 @ CHECK: vmovn.i64 d16, q8 @ encoding: [0x20,0x02,0xfa,0xf3]
/external/capstone/suite/MC/ARM/
Dneont2-mov-encoding.s.cs36 0xf2,0xff,0x20,0x02 = vmovn.i16 d16, q8
37 0xf6,0xff,0x20,0x02 = vmovn.i32 d16, q8
38 0xfa,0xff,0x20,0x02 = vmovn.i64 d16, q8
Dneon-mov-encoding.s.cs36 0x20,0x02,0xf2,0xf3 = vmovn.i16 d16, q8
37 0x20,0x02,0xf6,0xf3 = vmovn.i32 d16, q8
38 0x20,0x02,0xfa,0xf3 = vmovn.i64 d16, q8
/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/
Dvmovn.ll189 …%2 = tail call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %…
213 …%2 = tail call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %…
237 …%2 = tail call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %…
261 …%2 = tail call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %…
285 …%2 = tail call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %…
309 …%2 = tail call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %…
333 …%2 = tail call <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8> %a, <8 x i16> %…
357 …%2 = tail call <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16> %a, <4 x i32> %…
365 declare <16 x i8> @llvm.arm.mve.vmovn.predicated.v16i8.v8i16.v8i1(<16 x i8>, <8 x i16>, i32, <8 x i…
366 declare <8 x i16> @llvm.arm.mve.vmovn.predicated.v8i16.v4i32.v4i1(<8 x i16>, <4 x i32>, i32, <4 x i…
/external/libavc/common/arm/
Dih264_resi_trans_quant_a9.s207 vmovn.s32 d30, q11 @Narrow row 1
208 vmovn.s32 d31, q12 @Narrow row 2
209 vmovn.s32 d0 , q13 @Narrow row 3
210 vmovn.s32 d1 , q14 @Narrow row 4
222 vmovn.u16 d14, q5 @I Narrow the comparison for row 1 and 2 blk 1
223 vmovn.u16 d15, q6 @I Narrow the comparison for row 1 and 2 blk 2
402 vmovn.s32 d30, q11 @Narrow row 1
403 vmovn.s32 d31, q12 @Narrow row 2
404 vmovn.s32 d0 , q13 @Narrow row 3
405 vmovn.s32 d1 , q14 @Narrow row 4
[all …]

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