1; RUN: llc -mtriple arm-eabi -mattr=+neon -disable-post-ra -pre-RA-sched source %s -o - | FileCheck %s 2; RUN: llc -mtriple thumbv7-windows-itanium -mattr=+neon -disable-post-ra -pre-RA-sched source %s -o - | FileCheck %s 3 4define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { 5 %tmp1 = load <8 x i8>, <8 x i8>* %A 6 %tmp2 = load <8 x i8>, <8 x i8>* %B 7 %tmp3 = sdiv <8 x i8> %tmp1, %tmp2 8 ret <8 x i8> %tmp3 9} 10 11; CHECK-LABEL: sdivi8: 12; CHECK: vrecpe.f32 13; CHECK: vmovn.i32 14; CHECK: vrecpe.f32 15; CHECK: vmovn.i32 16; CHECK: vmovn.i16 17 18define <8 x i8> @udivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { 19 %tmp1 = load <8 x i8>, <8 x i8>* %A 20 %tmp2 = load <8 x i8>, <8 x i8>* %B 21 %tmp3 = udiv <8 x i8> %tmp1, %tmp2 22 ret <8 x i8> %tmp3 23} 24 25; CHECK-LABEL: udivi8: 26; CHECK: vrecpe.f32 27; CHECK: vrecps.f32 28; CHECK: vmovn.i32 29; CHECK: vrecpe.f32 30; CHECK: vrecps.f32 31; CHECK: vmovn.i32 32; CHECK: vqmovun.s16 33 34define <4 x i16> @sdivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { 35 %tmp1 = load <4 x i16>, <4 x i16>* %A 36 %tmp2 = load <4 x i16>, <4 x i16>* %B 37 %tmp3 = sdiv <4 x i16> %tmp1, %tmp2 38 ret <4 x i16> %tmp3 39} 40 41; CHECK-LABEL: sdivi16: 42; CHECK: vrecpe.f32 43; CHECK: vrecps.f32 44; CHECK: vmovn.i32 45 46define <4 x i16> @udivi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { 47 %tmp1 = load <4 x i16>, <4 x i16>* %A 48 %tmp2 = load <4 x i16>, <4 x i16>* %B 49 %tmp3 = udiv <4 x i16> %tmp1, %tmp2 50 ret <4 x i16> %tmp3 51} 52 53; CHECK-LABEL: udivi16: 54; CHECK: vrecpe.f32 55; CHECK: vrecps.f32 56; CHECK: vrecps.f32 57; CHECK: vmovn.i32 58 59