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/external/llvm-project/llvm/test/CodeGen/ARM/
Dneon-v8.1a.ll6 declare <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16>, <4 x i16>)
7 declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>)
8 declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>)
9 declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>)
23 %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %mhs, <4 x i16> %rhs)
31 %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)
39 %prod = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %mhs, <2 x i32> %rhs)
47 %prod = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs)
55 %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %mhs, <4 x i16> %rhs)
63 %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)
[all …]
Dvqdmul.ll85 ;CHECK: vqrdmulh.s16
88 %tmp3 = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
94 ;CHECK: vqrdmulh.s32
97 %tmp3 = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
103 ;CHECK: vqrdmulh.s16
106 %tmp3 = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
112 ;CHECK: vqrdmulh.s32
115 %tmp3 = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
122 ; CHECK: vqrdmulh.s16 q0, q0, d2[1]
124 …%1 = tail call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %arg0_int16x8_t, <8 x i16> %0) ; …
[all …]
/external/llvm/test/CodeGen/ARM/
Dneon-v8.1a.ll6 declare <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16>, <4 x i16>)
7 declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>)
8 declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>)
9 declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>)
23 %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %mhs, <4 x i16> %rhs)
31 %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)
39 %prod = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %mhs, <2 x i32> %rhs)
47 %prod = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs)
55 %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %mhs, <4 x i16> %rhs)
63 %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)
[all …]
Dvqdmul.ll85 ;CHECK: vqrdmulh.s16
88 %tmp3 = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
94 ;CHECK: vqrdmulh.s32
97 %tmp3 = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
103 ;CHECK: vqrdmulh.s16
106 %tmp3 = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
112 ;CHECK: vqrdmulh.s32
115 %tmp3 = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
122 ; CHECK: vqrdmulh.s16 q0, q0, d2[1]
124 …%1 = tail call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %arg0_int16x8_t, <8 x i16> %0) ; …
[all …]
/external/llvm/test/MC/ARM/
Dneont2-mul-encoding.s43 vqrdmulh.s16 d16, d16, d17
44 vqrdmulh.s32 d16, d16, d17
45 vqrdmulh.s16 q8, q8, q9
46 vqrdmulh.s32 q8, q8, q9
48 @ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xff,0xa1,0x0b]
49 @ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x0b]
50 @ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xff,0xe2,0x0b]
51 @ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x0b]
Dneon-mul-encoding.s71 vqrdmulh.s16 d16, d16, d17
72 vqrdmulh.s32 d16, d16, d17
73 vqrdmulh.s16 q8, q8, q9
74 vqrdmulh.s32 q8, q8, q9
76 @ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf3]
77 @ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf3]
78 @ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf3]
79 @ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf3]
/external/llvm-project/llvm/test/MC/ARM/
Dneont2-mul-encoding.s43 vqrdmulh.s16 d16, d16, d17
44 vqrdmulh.s32 d16, d16, d17
45 vqrdmulh.s16 q8, q8, q9
46 vqrdmulh.s32 q8, q8, q9
48 @ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xff,0xa1,0x0b]
49 @ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x0b]
50 @ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xff,0xe2,0x0b]
51 @ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x0b]
Dneon-mul-encoding.s71 vqrdmulh.s16 d16, d16, d17
72 vqrdmulh.s32 d16, d16, d17
73 vqrdmulh.s16 q8, q8, q9
74 vqrdmulh.s32 q8, q8, q9
76 @ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf3]
77 @ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf3]
78 @ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf3]
79 @ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf3]
Dmve-integer.s62 # CHECK: vqrdmulh.s8 q0, q5, q5 @ encoding: [0x0a,0xff,0x4a,0x0b]
63 vqrdmulh.s8 q0, q5, q5
65 # CHECK: vqrdmulh.s16 q1, q4, q2 @ encoding: [0x18,0xff,0x44,0x2b]
66 vqrdmulh.s16 q1, q4, q2
68 # CHECK: vqrdmulh.s32 q0, q5, q0 @ encoding: [0x2a,0xff,0x40,0x0b]
69 vqrdmulh.s32 q0, q5, q0
Dmve-qdest-rsrc.s299 # CHECK: vqrdmulh.s8 q0, q2, r6 @ encoding: [0x05,0xfe,0x66,0x0e]
300 # CHECK-NOFP: vqrdmulh.s8 q0, q2, r6 @ encoding: [0x05,0xfe,0x66,0x0e]
301 vqrdmulh.s8 q0, q2, r6
303 # CHECK: vqrdmulh.s16 q0, q0, r2 @ encoding: [0x11,0xfe,0x62,0x0e]
304 # CHECK-NOFP: vqrdmulh.s16 q0, q0, r2 @ encoding: [0x11,0xfe,0x62,0x0e]
305 vqrdmulh.s16 q0, q0, r2
307 # CHECK: vqrdmulh.s32 q0, q0, r2 @ encoding: [0x21,0xfe,0x62,0x0e]
308 # CHECK-NOFP: vqrdmulh.s32 q0, q0, r2 @ encoding: [0x21,0xfe,0x62,0x0e]
309 vqrdmulh.s32 q0, q0, r2
/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/
Dvqrdmulhq.ll7 ; CHECK-NEXT: vqrdmulh.s8 q0, q0, q1
10 %0 = tail call <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8> %a, <16 x i8> %b)
14 declare <16 x i8> @llvm.arm.mve.vqrdmulh.v16i8(<16 x i8>, <16 x i8>) #1
19 ; CHECK-NEXT: vqrdmulh.s16 q0, q0, q1
22 %0 = tail call <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16> %a, <8 x i16> %b)
26 declare <8 x i16> @llvm.arm.mve.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) #1
31 ; CHECK-NEXT: vqrdmulh.s32 q0, q0, q1
34 %0 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %a, <4 x i32> %b)
38 declare <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) #1
97 ; CHECK-NEXT: vqrdmulh.s8 q0, q0, r0
[all …]
/external/llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
Dremat-vctp.ll24 ; CHECK-NEXT: vqrdmulh.s32 q6, q7, q5
26 ; CHECK-NEXT: vqrdmulh.s32 q6, q7, q6
28 ; CHECK-NEXT: vqrdmulh.s32 q5, q6, q5
30 ; CHECK-NEXT: vqrdmulh.s32 q5, q6, q5
35 ; CHECK-NEXT: vqrdmulh.s32 q4, q4, q5
66 %i26 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i25, <4 x i32> %i21)
68 %i28 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i25, <4 x i32> %i27)
70 %i30 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i29, <4 x i32> %i21)
72 %i32 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i29, <4 x i32> %i31)
75 %i35 = tail call <4 x i32> @llvm.arm.mve.vqrdmulh.v4i32(<4 x i32> %i14, <4 x i32> %i34)
[all …]
/external/capstone/suite/MC/ARM/
Dneont2-mul-encoding.s.cs18 0x50,0xff,0xa1,0x0b = vqrdmulh.s16 d16, d16, d17
19 0x60,0xff,0xa1,0x0b = vqrdmulh.s32 d16, d16, d17
20 0x50,0xff,0xe2,0x0b = vqrdmulh.s16 q8, q8, q9
21 0x60,0xff,0xe2,0x0b = vqrdmulh.s32 q8, q8, q9
Dneon-mul-encoding.s.cs32 0xa1,0x0b,0x50,0xf3 = vqrdmulh.s16 d16, d16, d17
33 0xa1,0x0b,0x60,0xf3 = vqrdmulh.s32 d16, d16, d17
34 0xe2,0x0b,0x50,0xf3 = vqrdmulh.s16 q8, q8, q9
35 0xe2,0x0b,0x60,0xf3 = vqrdmulh.s32 q8, q8, q9
/external/arm-neon-tests/
Dref_vqrdmulh_n.c34 #define INSN vqrdmulh
DMakefile.gcc51 vshr_n vsra_n vtrn vuzp vzip vreinterpret vqdmulh vqrdmulh \
Dref_vqrdmulh_lane.c34 #define INSN vqrdmulh
Dref_vqrdmulh.c34 #define INSN vqrdmulh
DMakefile45 vshr_n vsra_n vtrn vuzp vzip vreinterpret vqdmulh vqrdmulh \
/external/llvm/test/MC/Disassembler/ARM/
Dneon-tests.txt45 # CHECK: vqrdmulh.s32 d0, d0, d3[1]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dneon-tests.txt48 # CHECK: vqrdmulh.s32 d0, d0, d3[1]
Dmve-integer.txt93 # CHECK: vqrdmulh.s8 q0, q5, q5 @ encoding: [0x0a,0xff,0x4a,0x0b]
97 # CHECK: vqrdmulh.s16 q1, q4, q2 @ encoding: [0x18,0xff,0x44,0x2b]
101 # CHECK: vqrdmulh.s32 q0, q5, q0 @ encoding: [0x2a,0xff,0x40,0x0b]
Dmve-qdest-rsrc.txt298 # CHECK: vqrdmulh.s8 q0, q2, r6 @ encoding: [0x05,0xfe,0x66,0x0e]
302 # CHECK: vqrdmulh.s16 q0, q0, r2 @ encoding: [0x11,0xfe,0x62,0x0e]
306 # CHECK: vqrdmulh.s32 q0, q0, r2 @ encoding: [0x21,0xfe,0x62,0x0e]
/external/clang/include/clang/Basic/
Darm_neon.td376 def OP_QRDMULH_LN : Op<(call "vqrdmulh", $p0, (splat $p1, $p2))>;
377 def OP_QRDMLAH : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, $p2))>;
378 def OP_QRDMLSH : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, $p2))>;
379 def OP_QRDMLAH_LN : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, (splat $p2, $p3)))>;
380 def OP_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, (splat $p2, $p3)))>;
479 def OP_SCALAR_QRDMULH_LN : ScalarMulOp<"vqrdmulh">;
481 def OP_SCALAR_QRDMLAH_LN : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1,
483 def OP_SCALAR_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1,
526 def VQRDMULH : SInst<"vqrdmulh", "ddd", "siQsQi">;
1438 def SCALAR_SQRDMULH : SInst<"vqrdmulh", "sss", "SsSi">;
/external/llvm-project/clang/include/clang/Basic/
Darm_neon.td81 def OP_QRDMULH_LN : Op<(call "vqrdmulh", $p0, (call_mangled "splat_lane", $p1, $p2))>;
82 def OP_QRDMULH_N : Op<(call "vqrdmulh", $p0, (dup $p1))>;
83 def OP_QRDMLAH : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, $p2))>;
84 def OP_QRDMLSH : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, $p2))>;
85 def OP_QRDMLAH_LN : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, (call_mangled "splat_lane", $p2, …
86 def OP_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, (call_mangled "splat_lane", $p2, …
186 def OP_SCALAR_QRDMULH_LN : ScalarMulOp<"vqrdmulh">;
188 def OP_SCALAR_QRDMLAH_LN : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1,
190 def OP_SCALAR_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1,
326 def VQRDMULH : SInst<"vqrdmulh", "...", "siQsQi">;
[all …]

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