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/external/llvm/test/CodeGen/AArch64/
Darm64-ldp-cluster.ll9 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
10 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
14 ; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
15 ; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
29 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRSWui
30 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRSWui
34 ; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRSWui
35 ; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRSWui
50 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDURWi
51 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDURWi
[all …]
Dtailcall_misched_graph.ll29 ; CHECK: [[VRA:%vreg.*]]<def> = LDRXui <fi#-1>
30 ; CHECK: [[VRB:%vreg.*]]<def> = LDRXui <fi#-2>
31 ; CHECK: STRXui %vreg{{.*}}, <fi#-4>
43 ; CHECK: SU([[DEPSTOREA]]): STRXui %vreg{{.*}}, <fi#-4>
44 ; CHECK: SU([[DEPSTOREB]]): STRXui %vreg{{.*}}, <fi#-3>
Darm64-fast-isel-rem.ll7 ; CHECK-SSA: [[QUOTREG:%vreg[0-9]+]]<def> = SDIVWr
9 ; CHECK-SSA: {{%vreg[0-9]+}}<def> = MSUBWrrr [[QUOTREG]]
/external/bcc/src/lua/bpf/
Dbuiltins.lua79 e.emit(BPF.ALU + BPF.END + BPF.TO_BE, e.vreg(dst), 0, 0, w)
87 e.emit(BPF.ALU + BPF.END + BPF.TO_LE, e.vreg(dst), 0, 0, w)
114 local src_reg = e.vreg(b)
115 local dst_reg = e.vreg(a)
118 e.vreg(ret, 0, true, ffi.typeof('int32_t'))
152 e.vreg(src, 3)
161 e.vreg(ret, 0, true, ffi.typeof('int32_t'))
227 e.vreg(src, 3)
232 e.vreg(ret, 0, true, ffi.typeof('int32_t'))
271 e.vreg(e.tmpvar, 3+i-1) -- Materialize it in arg register
[all …]
Dbpf.lua197 local function vreg(var, reg, reserve, vtype) function
300 src_reg = vreg(a)
307 src_reg = vreg(a)
316 src_reg = vreg(a)
330 vreg(i)
337 vreg(i, Vcomp[i].reg)
383 local a_reg, b_reg = vreg(a), vreg(b)
410 local reg = vreg(a)
440 local dst_reg = vreg(dst)
460 local src_reg = b and vreg(b) or 0 -- SRC is optional for unary operations
[all …]
Dproto.lua229 dst_reg = e.vreg(var, 0, true)
233 tmp_reg = e.vreg(e.tmpvar, 0, true, type) -- Reserve R0 for temporary relative offset
234 dst_reg = e.vreg(var) -- Must rematerialize (if it was spilled by tmp var)
263 local dst_reg = e.vreg(var)
/external/mesa3d/src/gallium/drivers/r600/sb/
Dsb_bc_finalize.cpp516 unsigned vreg = v->gpr.sel(); in copy_fetch_src() local
520 reg = vreg; in copy_fetch_src()
521 else if ((unsigned)reg != vreg) { in copy_fetch_src()
623 unsigned vreg = v->gpr.sel(); in finalize_fetch() local
627 reg = vreg; in finalize_fetch()
628 else if ((unsigned)reg != vreg) { in finalize_fetch()
670 unsigned vreg = v->gpr.sel(); in finalize_fetch() local
674 reg = vreg; in finalize_fetch()
675 else if ((unsigned)reg != vreg) { in finalize_fetch()
747 unsigned vreg = v->gpr.sel(); in finalize_cf() local
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dquadint-return.ll17 ; CHECK: %X3<def> = COPY %vreg
18 ; CHECK-NEXT: %X4<def> = COPY %vreg
/external/llvm/test/CodeGen/ARM/
Dmisched-copy-arm.ll36 ; CHECK: %[[R4:vreg[0-9]+]]<def>, %[[R1:vreg[0-9]+]]<def,tied2> = t2LDR_PRE %[[R1]]<tied1>
37 ; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R1]]
38 ; CHECK: %vreg{{[0-9]+}}<def> = COPY %[[R4]]
Dfast-isel-shift-materialize.ll6 ; When materializing the '2' for the shifts below, the second shift kills the vreg
7 ; we materialize in to. However, the first shift was also killing that vreg.
Dfast-isel-remat-same-constant.ll7 ; generated by the GEPs. The first add generated killed the vreg for the #6680 constant which shou…
9 ; down. This meant the next use of the vreg for #6680 was after the first which had killed it.
/external/llvm-project/libc/AOR_v20.02/string/arm/
Dmemcpy.S86 .macro cpy_line_vfp vreg, base
87 vstr \vreg, [dst, #\base]
88 vldr \vreg, [src, #\base]
95 vstr \vreg, [dst, #\base + 32]
96 vldr \vreg, [src, #\base + prefetch_lines * 64 - 32]
105 .macro cpy_tail_vfp vreg, base
106 vstr \vreg, [dst, #\base]
107 vldr \vreg, [src, #\base]
114 vstr \vreg, [dst, #\base + 32]
/external/arm-optimized-routines/string/arm/
Dmemcpy.S85 .macro cpy_line_vfp vreg, base
86 vstr \vreg, [dst, #\base]
87 vldr \vreg, [src, #\base]
94 vstr \vreg, [dst, #\base + 32]
95 vldr \vreg, [src, #\base + prefetch_lines * 64 - 32]
104 .macro cpy_tail_vfp vreg, base
105 vstr \vreg, [dst, #\base]
106 vldr \vreg, [src, #\base]
113 vstr \vreg, [dst, #\base + 32]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dfast-isel-shift-materialize.ll6 ; When materializing the '2' for the shifts below, the second shift kills the vreg
7 ; we materialize in to. However, the first shift was also killing that vreg.
Dfast-isel-remat-same-constant.ll7 ; generated by the GEPs. The first add generated killed the vreg for the #6680 constant which shou…
9 ; down. This meant the next use of the vreg for #6680 was after the first which had killed it.
/external/llvm-project/llvm/test/CodeGen/MIR/X86/
Dmircanon-flags.mir2 # RUN: llc -march=x86-64 -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machin…
4 # naming collisions with the new vreg renamers naming scheme.
Dmir-canon-hash-bb.mir3 # RUN: llc -run-pass mir-namer -mir-vreg-namer-use-stable-hash -x mir -verify-machineinstrs %s -o …
4 # RUN: llc -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -x mir -verify-machineinstr…
Dmir-namer-hash-frameindex.mir2 # RUN: llc -mtriple x86_64-linux-gnu -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -v…
/external/llvm-project/llvm/test/CodeGen/X86/
Dfast-isel-bitcast-crash.ll4 ; This used to crash due to the bitcast in the entry block reusing the vreg
7 ; was fixed by emitting a reg-reg copy for the bitcast so the vreg type will
/external/vixl/test/aarch64/
Dtest-utils-aarch64.cc213 const VRegister& vreg) { in Equal128() argument
214 VIXL_ASSERT(vreg.Is128Bits()); in Equal128()
218 QRegisterValue result = core->qreg(vreg.GetCode()); in Equal128()
291 const VRegister& vreg) { in Equal64() argument
292 VIXL_ASSERT(vreg.Is64Bits()); in Equal64()
293 uint64_t result = core->dreg_bits(vreg.GetCode()); in Equal64()
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoVPseudos.td219 defvar vreg = lmul.vrclass;
231 : Pseudo<(outs vreg:$rd),
232 (ins vreg:$merge, GPR:$rs1, VMaskOp:$mask, GPR:$vl,
248 (ins vreg:$rd, GPR:$rs1, VMaskOp:$mask, GPR:$vl,
/external/llvm-project/llvm/test/CodeGen/MIR/Generic/
DCFPImmMIRCanonHash.mir2 # RUN: llc -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs -o - %…
/external/llvm-project/llvm/test/CodeGen/MIR/AArch64/
Dmir-canon-constant-pool-hash.mir2 # RUN: llc -o - -run-pass mir-canonicalizer -mir-vreg-namer-use-stable-hash -verify-machineinstrs %…
/external/llvm-project/llvm/docs/GlobalISel/
DIRTranslator.rst69 Aggregates are lowered to a single scalar vreg.
76 See `PR26161 <https://llvm.org/PR26161>`_: [GlobalISel] Value to vreg during
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dgreedy-broken-ssa-verifier-error.mir4 # introduces vreg defs when the MIR parser infers SSA.

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