• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1# RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs -run-pass=greedy -stress-regalloc=2 %s -o - | FileCheck -check-prefix=GCN %s
2
3# Make sure there's no verifier error after register allocation
4# introduces vreg defs when the MIR parser infers SSA.
5
6---
7name: ra_introduces_vreg_def
8tracksRegLiveness: true
9machineFunctionInfo:
10  scratchRSrcReg:  '$sgpr0_sgpr1_sgpr2_sgpr3'
11  frameOffsetReg:  '$sgpr33'
12  stackPtrOffsetReg: '$sgpr32'
13  argumentInfo:
14    privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
15body:             |
16  ; GCN-LABEL: name: ra_introduces_vreg_def
17  ; GCN: [[COPY_V0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
18  ; GCN: [[COPY_V0]]:vgpr_32 =
19  bb.0:
20    liveins: $vgpr0, $vgpr1
21    %0:vgpr_32 = COPY $vgpr0
22    %1:vgpr_32 = COPY $vgpr1
23    S_NOP 0, implicit %0
24    S_NOP 0, implicit %1
25
26  bb.1:
27    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
28    $vgpr1 = V_MOV_B32_e32 1, implicit $exec
29    S_NOP 0, implicit %0
30    S_NOP 0, implicit %1
31
32  bb.2:
33    S_CBRANCH_EXECNZ %bb.1, implicit $exec
34
35  bb.3:
36    $exec_lo = S_OR_B32 $exec_lo, undef $sgpr4, implicit-def $scc
37    $vgpr0 = COPY %0
38    S_SETPC_B64_return undef $sgpr30_sgpr31, implicit $vgpr0
39
40...
41