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Searched refs:vsrd (Results 1 – 24 of 24) sorted by relevance

/external/llvm-project/llvm/test/MC/VE/
DVSRD.s6 # CHECK-INST: vsrd %v11, (%v22, %v23), %s20
8 vsrd %v11, (%v22, %v23), %s20 label
10 # CHECK-INST: vsrd %vix, (%vix, %vix), %s23
12 vsrd %vix, (%vix, %vix), %s23 label
14 # CHECK-INST: vsrd %vix, (%v22, %v30), 22
16 vsrd %vix, (%v22, %v30), 22 label
18 # CHECK-INST: vsrd %v11, (%v22, %vix), 127, %vm11
20 vsrd %v11, (%v22, %vix), 127, %vm11 label
22 # CHECK-INST: vsrd %v11, (%vix, %v22), 21, %vm11
24 vsrd %v11, (%vix, %v22), 21, %vm11 label
[all …]
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dvec-intrinsics-03.ll6 declare <16 x i8> @llvm.s390.vsrd(<16 x i8>, <16 x i8>, i32)
37 ; CHECK: vsrd %v24, %v24, %v26, 1
39 %res = call <16 x i8> @llvm.s390.vsrd(<16 x i8> %a, <16 x i8> %b, i32 1)
46 ; CHECK: vsrd %v24, %v24, %v26, 7
48 %res = call <16 x i8> @llvm.s390.vsrd(<16 x i8> %a, <16 x i8> %b, i32 7)
/external/llvm/test/CodeGen/PowerPC/
Dvec_rotate_shift.ll7 declare <2 x i64> @llvm.ppc.altivec.vsrd(<2 x i64>, <2 x i64>) nounwind readnone
27 ; CHECK: vsrd 2, 2, 3
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dvec_rotate_shift.ll7 declare <2 x i64> @llvm.ppc.altivec.vsrd(<2 x i64>, <2 x i64>) nounwind readnone
27 ; CHECK: vsrd 2, 2, 3
Dpr47891.ll47 ; CHECK-NEXT: vsrd v3, v4, v3
Dshift_mask.ll168 ; CHECK-NEXT: vsrd 2, 2, 3
Dvsx.ll1922 ; CHECK-LE-NEXT: vsrd v2, v2, v3
/external/llvm-project/llvm/test/MC/SystemZ/
Dinsn-good-z15.s952 #CHECK: vsrd %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x87]
953 #CHECK: vsrd %v0, %v0, %v0, 255 # encoding: [0xe7,0x00,0x00,0xff,0x00,0x87]
954 #CHECK: vsrd %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x87]
955 #CHECK: vsrd %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x87]
956 #CHECK: vsrd %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x87]
957 #CHECK: vsrd %v13, %v17, %v21, 121 # encoding: [0xe7,0xd1,0x50,0x79,0x06,0x87]
959 vsrd %v0, %v0, %v0, 0
960 vsrd %v0, %v0, %v0, 255
961 vsrd %v0, %v0, %v31, 0
962 vsrd %v0, %v31, %v0, 0
[all …]
Dinsn-bad-z15.s555 #CHECK: vsrd %v0, %v0, %v0, -1
557 #CHECK: vsrd %v0, %v0, %v0, 256
559 vsrd %v0, %v0, %v0, -1
560 vsrd %v0, %v0, %v0, 256
Dinsn-bad-z14.s783 #CHECK: vsrd %v0, %v0, %v0, 0
785 vsrd %v0, %v0, %v0, 0
/external/llvm-project/llvm/test/MC/Disassembler/SystemZ/
Dinsns-z15.txt974 # CHECK: vsrd %v0, %v0, %v0, 0
977 # CHECK: vsrd %v0, %v0, %v0, 255
980 # CHECK: vsrd %v0, %v0, %v31, 0
983 # CHECK: vsrd %v0, %v31, %v0, 0
986 # CHECK: vsrd %v31, %v0, %v0, 0
989 # CHECK: vsrd %v13, %v17, %v21, 121
/external/llvm-project/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s604 # CHECK-BE: vsrd 2, 3, 4 # encoding: [0x10,0x43,0x26,0xc4]
605 # CHECK-LE: vsrd 2, 3, 4 # encoding: [0xc4,0x26,0x43,0x10]
606 vsrd 2, 3, 4
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s595 # CHECK-BE: vsrd 2, 3, 4 # encoding: [0x10,0x43,0x26,0xc4]
596 # CHECK-LE: vsrd 2, 3, 4 # encoding: [0xc4,0x26,0x43,0x10]
597 vsrd 2, 3, 4
/external/llvm-project/llvm/test/Verifier/SystemZ/
Dintrinsic-immarg.ll393 declare <16 x i8> @llvm.s390.vsrd(<16 x i8>, <16 x i8>, i32)
397 ; CHECK-NEXT: %res = call <16 x i8> @llvm.s390.vsrd(<16 x i8> %a, <16 x i8> %b, i32 %c)
398 %res = call <16 x i8> @llvm.s390.vsrd(<16 x i8> %a, <16 x i8> %b, i32 %c)
/external/llvm-project/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt549 # CHECK: vsrd 2, 3, 4
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt546 # CHECK: vsrd 2, 3, 4
/external/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td1067 "vsrd $vD, $vA, $vB", IIC_VecGeneral,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZInstrVector.td802 def VSRD : TernaryVRId<"vsrd", 0xE787, int_s390_vsrd, v128b, v128b, 0>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td1180 "vsrd $vD, $vA, $vB", IIC_VecGeneral, []>;
/external/llvm-project/llvm/lib/Target/VE/
DVEInstrVec.td1022 defm VSRD : RVSDm<"vsrd", 0xf4, V64, VM>;
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZInstrVector.td829 def VSRD : TernaryVRId<"vsrd", 0xE787, int_s390_vsrd, v128b, v128b, 0>;
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrAltivec.td1207 "vsrd $vD, $vA, $vB", IIC_VecGeneral, []>;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4388 "aw\004vsrb\004vsrd\004vsrh\004vsro\004vsrv\004vsrw\007vsubcuq\007vsubcu"
6751 …{ 12143 /* vsrd */, PPC::VSRD, Convert__RegVRRC1_0__RegVRRC1_1__RegVRRC1_2, AMFBS_None, { MCK_RegV…
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc6280 "llvm.s390.vsrd",
16413 29, // llvm.s390.vsrd