| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | prelegalizercombiner-trivial-arith.mir | 8 liveins: $w0
12 ; CHECK: liveins: $w0
13 ; CHECK: %x:_(s32) = COPY $w0
14 ; CHECK: $w0 = COPY %x(s32)
15 ; CHECK: RET_ReallyLR implicit $w0
16 %x:_(s32) = COPY $w0
19 $w0 = COPY %op(s32)
20 RET_ReallyLR implicit $w0
28 liveins: $w0
32 ; CHECK: liveins: $w0
[all …]
|
| D | opt-shifted-reg-compare.mir | 20 liveins: $w0, $w1
23 ; CHECK: liveins: $w0, $w1
24 ; CHECK: %copy0:gpr32 = COPY $w0
28 ; CHECK: $w0 = COPY %cmp
29 ; CHECK: RET_ReallyLR implicit $w0
30 %copy0:gpr(s32) = COPY $w0
35 $w0 = COPY %cmp(s32)
36 RET_ReallyLR implicit $w0
46 liveins: $w0, $w1
49 ; CHECK: liveins: $w0, $w1
[all …]
|
| D | prelegalizercombiner-select.mir | 16 liveins: $w0, $w1
19 ; CHECK: liveins: $w0, $w1
20 ; CHECK: %a:_(s32) = COPY $w0
21 ; CHECK: $w0 = COPY %a(s32)
22 ; CHECK: RET_ReallyLR implicit $w0
23 %a:_(s32) = COPY $w0
27 $w0 = COPY %select(s32)
28 RET_ReallyLR implicit $w0
36 liveins: $w0, $w1
43 ; CHECK: liveins: $w0, $w1
[all …]
|
| D | select-cmp.mir | 10 liveins: $w0
13 ; CHECK: liveins: $w0
14 ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
17 ; CHECK: $w0 = COPY [[CSINCWr]]
18 ; CHECK: RET_ReallyLR implicit $w0
19 %0:gpr(s32) = COPY $w0
22 $w0 = COPY %5(s32)
23 RET_ReallyLR implicit $w0
40 ; CHECK: $w0 = COPY [[CSINCWr]]
41 ; CHECK: RET_ReallyLR implicit $w0
[all …]
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| D | postlegalizer-lowering-adjust-icmp-imm.mir | 14 liveins: $w0
22 ; LOWER: liveins: $w0
23 ; LOWER: %reg:_(s32) = COPY $w0
26 ; LOWER: $w0 = COPY %cmp(s32)
27 ; LOWER: RET_ReallyLR implicit $w0
29 ; SELECT: liveins: $w0
30 ; SELECT: %reg:gpr32sp = COPY $w0
33 ; SELECT: $w0 = COPY %cmp
34 ; SELECT: RET_ReallyLR implicit $w0
35 %reg:_(s32) = COPY $w0
[all …]
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| D | select-select.mir | 14 liveins: $s0, $s1, $w0
17 ; CHECK: liveins: $s0, $s1, $w0
18 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
27 %3:gpr(s32) = COPY $w0
46 liveins: $d0, $d1, $w0
49 ; CHECK: liveins: $d0, $d1, $w0
50 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
59 %3:gpr(s32) = COPY $w0
75 liveins: $w0, $w1, $w2, $w3
77 ; CHECK: liveins: $w0, $w1, $w2, $w3
[all …]
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| D | prelegalizercombiner-xor-of-and-with-same-reg.mir | 11 liveins: $w0, $w1
14 ; CHECK: liveins: $w0, $w1
15 ; CHECK: %x:_(s32) = COPY $w0
20 ; CHECK: $w0 = COPY %xor(s32)
21 ; CHECK: RET_ReallyLR implicit $w0
22 %x:_(s32) = COPY $w0
26 $w0 = COPY %xor(s32)
27 RET_ReallyLR implicit $w0
60 liveins: $w0, $w1
63 ; CHECK: liveins: $w0, $w1
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | post-ra-machine-sink.mir | 7 # CHECK-NOT: $w19 = COPY killed $w0
9 # CHECK: liveins: $w0, $w1
10 # CHECK: renamable $w19 = COPY killed $w0
16 liveins: $w0, $w1
18 renamable $w19 = COPY killed $w0
24 $w0 = ADDWrr $w1, $w19
28 $w0 = COPY $wzr
36 # CHECK-NOT: renamable $w19 = COPY killed $w0
38 # CHECK: liveins: $w0, $w1
39 # CHECK: renamable $w19 = COPY killed $w0
[all …]
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| D | mul_pow2.ll | 13 ; CHECK-NEXT: lsl w0, w0, #1
18 ; GISEL-NEXT: lsl w0, w0, #1
28 ; CHECK-NEXT: add w0, w0, w0, lsl #1
33 ; GISEL-NEXT: add w0, w0, w0, lsl #1
43 ; CHECK-NEXT: lsl w0, w0, #2
48 ; GISEL-NEXT: lsl w0, w0, #2
58 ; CHECK-NEXT: add w0, w0, w0, lsl #2
63 ; GISEL-NEXT: add w0, w0, w0, lsl #2
74 ; CHECK-NEXT: add w8, w0, w0, lsl #1
75 ; CHECK-NEXT: lsl w0, w8, #1
[all …]
|
| D | falkor-hwpf-fix.mir | 13 liveins: $w0, $x1
18 $w0 = SUBWri $w0, 1, 0
19 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
34 liveins: $w0, $x1, $q2
39 $w0 = SUBWri $w0, 1, 0
40 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
55 liveins: $w0, $x1, $q2
58 $w0 = LDRWui $x1, 0
60 $w0 = SUBWri $w0, 1, 0
61 $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
[all …]
|
| D | machine-zero-copy-remove.mir | 4 # CHECK: ANDSWri $w0, 1, implicit-def $nzcv
11 liveins: $w0, $x1, $x2
13 $w0 = ANDSWri $w0, 1, implicit-def $nzcv
14 STRWui killed $w0, killed $x1, 0
21 $w0 = COPY $wzr
22 STRWui killed $w0, killed $x2, 0
52 # CHECK: ADDSWri $w0, 1, 0, implicit-def $nzcv
59 liveins: $w0, $x1, $x2
61 $w0 = ADDSWri $w0, 1, 0, implicit-def $nzcv
62 STRWui killed $w0, killed $x1, 0
[all …]
|
| D | pull-binop-through-shift.ll | 9 ; CHECK-NEXT: lsl w8, w0, #8
10 ; CHECK-NEXT: and w0, w8, #0xff000000
11 ; CHECK-NEXT: str w0, [x1]
21 ; CHECK-NEXT: lsl w8, w0, #8
22 ; CHECK-NEXT: and w0, w8, #0xff000000
23 ; CHECK-NEXT: str w0, [x1]
34 ; CHECK-NEXT: lsl w8, w0, #8
35 ; CHECK-NEXT: orr w0, w8, #0xff000000
36 ; CHECK-NEXT: str w0, [x1]
46 ; CHECK-NEXT: lsl w8, w0, #8
[all …]
|
| D | pull-conditional-binop-through-shift.ll | 9 ; CHECK-NEXT: and w8, w0, #0xff0000
11 ; CHECK-NEXT: csel w8, w8, w0, ne
12 ; CHECK-NEXT: lsl w0, w8, #8
13 ; CHECK-NEXT: str w0, [x2]
24 ; CHECK-NEXT: and w8, w0, #0xff0000
26 ; CHECK-NEXT: csel w8, w8, w0, ne
27 ; CHECK-NEXT: lsl w0, w8, #8
28 ; CHECK-NEXT: str w0, [x2]
40 ; CHECK-NEXT: orr w8, w0, #0xff0000
42 ; CHECK-NEXT: csel w8, w8, w0, ne
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/Mips/msa/ |
| D | avoid_vector_shift_combines.ll | 16 ; MIPSEL64R6-NEXT: ld.d $w0, 0($4)
17 ; MIPSEL64R6-NEXT: srli.d $w0, $w0, 52
18 ; MIPSEL64R6-NEXT: slli.d $w0, $w0, 51
20 ; MIPSEL64R6-NEXT: st.d $w0, 0($5)
24 ; MIPSEL32R5-NEXT: ld.d $w0, 0($4)
25 ; MIPSEL32R5-NEXT: srli.d $w0, $w0, 52
26 ; MIPSEL32R5-NEXT: slli.d $w0, $w0, 51
28 ; MIPSEL32R5-NEXT: st.d $w0, 0($5)
41 ; MIPSEL64R6-NEXT: ld.d $w0, 0($4)
42 ; MIPSEL64R6-NEXT: srli.d $w0, $w0, 6
[all …]
|
| D | arithmetic.ll | 8 ; ALL-NEXT: ld.b $w0, 0($6)
10 ; ALL-NEXT: addv.b $w0, $w1, $w0
12 ; ALL-NEXT: st.b $w0, 0($4)
23 ; ALL-NEXT: ld.h $w0, 0($6)
25 ; ALL-NEXT: addv.h $w0, $w1, $w0
27 ; ALL-NEXT: st.h $w0, 0($4)
38 ; ALL-NEXT: ld.w $w0, 0($6)
40 ; ALL-NEXT: addv.w $w0, $w1, $w0
42 ; ALL-NEXT: st.w $w0, 0($4)
53 ; ALL-NEXT: ld.d $w0, 0($6)
[all …]
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| D | f16-llvm-ir.ll | 115 ; MIPS32-NEXT: fill.h $w0, $2
116 ; MIPS32-NEXT: fexupr.w $w0, $w0
117 ; MIPS32-NEXT: copy_s.w $2, $w0[0]
133 ; MIPS64-N32-NEXT: fill.h $w0, $2
134 ; MIPS64-N32-NEXT: fexupr.w $w0, $w0
135 ; MIPS64-N32-NEXT: copy_s.w $2, $w0[0]
151 ; MIPS64-N64-NEXT: fill.h $w0, $2
152 ; MIPS64-N64-NEXT: fexupr.w $w0, $w0
153 ; MIPS64-N64-NEXT: copy_s.w $2, $w0[0]
183 ; MIPS32-NEXT: fill.h $w0, $2
[all …]
|
| /external/llvm/test/MC/AArch64/ |
| D | armv8.1a-atomic.s | 6 casb w0, w1, [x2]
7 casab w0, w1, [x2]
8 caslb w0, w1, [x2]
9 casalb w0, w1, [x2]
16 casb w0, w1, [w2]
26 cash w0, w1, [x2]
27 casah w0, w1, [x2]
28 caslh w0, w1, [x2]
29 casalh w0, w1, [x2]
37 cas w0, w1, [x2]
[all …]
|
| D | ldr-pseudo.s | 26 ldr w0, =0x10001
33 ldr w0, =0x10002
39 ldr w0, =0x10003
48 ldr w0, =0x10004
57 ldr w0, =0x10004
70 ldr w0, =0x10006
87 ldr w0, =0x10007
100 ldr w0, =foo
107 ldr w0, =f5
114 ldr w0, =f12
[all …]
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | armv8.1a-atomic.s | 6 casb w0, w1, [x2]
7 casab w0, w1, [x2]
8 caslb w0, w1, [x2]
9 casalb w0, w1, [x2]
16 casb w0, w1, [w2]
26 cash w0, w1, [x2]
27 casah w0, w1, [x2]
28 caslh w0, w1, [x2]
29 casalh w0, w1, [x2]
37 cas w0, w1, [x2]
[all …]
|
| D | label-arithmetic-elf.s | 8 adds w0, w1, #(end - start)
10 add w0, w1, #(end - start)
12 cmp w0, #(end - start)
14 sub w0, w1, #(end - start)
27 add w0, w1, #(end - start), lsl #12
28 cmp w0, #(end - start), lsl #12
32 add w0, w1, #((end - start) >> 2)
33 cmp w0, #((end - start) >> 2)
37 add w0, w1, #(end - start + 12)
38 cmp w0, #(end - start + 12)
[all …]
|
| D | ldr-pseudo.s | 26 ldr w0, =0x10001
33 ldr w0, =0x10002
39 ldr w0, =0x10003
48 ldr w0, =0x10004
57 ldr w0, =0x10004
70 ldr w0, =0x10006
87 ldr w0, =0x10007
100 ldr w0, =foo
107 ldr w0, =f5
114 ldr w0, =f12
[all …]
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| /external/llvm/test/CodeGen/AArch64/ |
| D | mul_pow2.ll | 8 ; CHECK: lsl w0, w0, #1
16 ; CHECK: add w0, w0, w0, lsl #1
24 ; CHECK: lsl w0, w0, #2
32 ; CHECK: add w0, w0, w0, lsl #2
41 ; CHECK: lsl {{w[0-9]+}}, w0, #3
42 ; CHECK: sub w0, {{w[0-9]+}}, w0
50 ; CHECK: lsl w0, w0, #3
58 ; CHECK: add w0, w0, w0, lsl #3
69 ; CHECK: neg w0, w0, lsl #1
77 ; CHECK: sub w0, w0, w0, lsl #2
[all …]
|
| D | arm64-fast-isel-icmp.ll | 6 ; CHECK: cmp w0, #31
7 ; CHECK-NEXT: cset w0, eq
16 ; CHECK: cmn w0, #7
17 ; CHECK-NEXT: cset w0, eq
26 ; CHECK: cmp w0, w1
27 ; CHECK-NEXT: cset w0, eq
36 ; CHECK: cmp w0, w1
37 ; CHECK-NEXT: cset w0, ne
66 ; CHECK: cmp w0, w1
67 ; CHECK-NEXT: cset w0, hi
[all …]
|
| /external/mesa3d/src/gallium/drivers/r600/sb/ |
| D | sb_bc_decoder.cpp | 54 CF_WORD0_EGCM w0(dw0); in decode_cf() local
55 bc.addr = w0.get_ADDR(); in decode_cf()
56 bc.jumptable_sel = w0.get_JUMPTABLE_SEL(); in decode_cf()
83 CF_WORD0_R6R7 w0(dw0); in decode_cf() local
84 bc.addr = w0.get_ADDR(); in decode_cf()
116 CF_ALU_WORD0_ALL w0(dw0); in decode_cf_alu() local
118 bc.kc[0].bank = w0.get_KCACHE_BANK0(); in decode_cf_alu()
119 bc.kc[1].bank = w0.get_KCACHE_BANK1(); in decode_cf_alu()
120 bc.kc[0].mode = w0.get_KCACHE_MODE0(); in decode_cf_alu()
122 bc.addr = w0.get_ADDR(); in decode_cf_alu()
[all …]
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| /external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Exynos/ |
| D | crc.s | 6 crc32w w0, w1, w2
7 crc32w w0, w0, w3
9 crc32cx w0, w1, x2
10 crc32cx w0, w0, x3
45 # M3-NEXT: 1 2 0.50 crc32w w0, w1, w2
46 # M3-NEXT: 1 2 0.50 crc32w w0, w0, w3
47 # M3-NEXT: 1 2 0.50 crc32cx w0, w1, x2
48 # M3-NEXT: 1 2 0.50 crc32cx w0, w0, x3
50 # M4-NEXT: 1 2 1.00 crc32w w0, w1, w2
51 # M4-NEXT: 1 2 1.00 crc32w w0, w0, w3
[all …]
|