1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-apple-darwin -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3 4... 5--- 6name: select_f32 7alignment: 4 8legalized: true 9regBankSelected: true 10tracksRegLiveness: true 11machineFunctionInfo: {} 12body: | 13 bb.0: 14 liveins: $s0, $s1, $w0 15 16 ; CHECK-LABEL: name: select_f32 17 ; CHECK: liveins: $s0, $s1, $w0 18 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 19 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0 20 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s1 21 ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY [[COPY]] 22 ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY3]] 23 ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY4]], 0, implicit-def $nzcv 24 ; CHECK: [[FCSELSrrr:%[0-9]+]]:fpr32 = FCSELSrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv 25 ; CHECK: $s0 = COPY [[FCSELSrrr]] 26 ; CHECK: RET_ReallyLR implicit $s0 27 %3:gpr(s32) = COPY $w0 28 %0:gpr(s1) = G_TRUNC %3(s32) 29 %1:fpr(s32) = COPY $s0 30 %2:fpr(s32) = COPY $s1 31 %5:fpr(s1) = COPY %0(s1) 32 %4:fpr(s32) = G_SELECT %5(s1), %1, %2 33 $s0 = COPY %4(s32) 34 RET_ReallyLR implicit $s0 35 36... 37--- 38name: select_f64 39alignment: 4 40legalized: true 41regBankSelected: true 42tracksRegLiveness: true 43machineFunctionInfo: {} 44body: | 45 bb.0: 46 liveins: $d0, $d1, $w0 47 48 ; CHECK-LABEL: name: select_f64 49 ; CHECK: liveins: $d0, $d1, $w0 50 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 51 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 52 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d1 53 ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY [[COPY]] 54 ; CHECK: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY3]] 55 ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY4]], 0, implicit-def $nzcv 56 ; CHECK: [[FCSELDrrr:%[0-9]+]]:fpr64 = FCSELDrrr [[COPY1]], [[COPY2]], 1, implicit $nzcv 57 ; CHECK: $d0 = COPY [[FCSELDrrr]] 58 ; CHECK: RET_ReallyLR implicit $d0 59 %3:gpr(s32) = COPY $w0 60 %0:gpr(s1) = G_TRUNC %3(s32) 61 %1:fpr(s64) = COPY $d0 62 %2:fpr(s64) = COPY $d1 63 %5:fpr(s1) = COPY %0(s1) 64 %4:fpr(s64) = G_SELECT %5(s1), %1, %2 65 $d0 = COPY %4(s64) 66 RET_ReallyLR implicit $d0 67... 68--- 69name: csel 70legalized: true 71regBankSelected: true 72tracksRegLiveness: true 73body: | 74 bb.0: 75 liveins: $w0, $w1, $w2, $w3 76 ; CHECK-LABEL: name: csel 77 ; CHECK: liveins: $w0, $w1, $w2, $w3 78 ; CHECK: %reg0:gpr32 = COPY $w0 79 ; CHECK: %reg1:gpr32 = COPY $w1 80 ; CHECK: %t:gpr32 = COPY $w2 81 ; CHECK: %f:gpr32 = COPY $w3 82 ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv 83 ; CHECK: %select:gpr32 = CSELWr %t, %f, 1, implicit $nzcv 84 ; CHECK: $w0 = COPY %select 85 ; CHECK: RET_ReallyLR implicit $w0 86 %reg0:gpr(s32) = COPY $w0 87 %reg1:gpr(s32) = COPY $w1 88 %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1 89 %cond:gpr(s1) = G_TRUNC %cmp(s32) 90 %t:gpr(s32) = COPY $w2 91 %f:gpr(s32) = COPY $w3 92 %select:gpr(s32) = G_SELECT %cond(s1), %t, %f 93 $w0 = COPY %select(s32) 94 RET_ReallyLR implicit $w0 95... 96--- 97name: csinc_t_0_f_1 98legalized: true 99regBankSelected: true 100tracksRegLiveness: true 101body: | 102 bb.0: 103 liveins: $w0, $w1 104 ; G_SELECT cc, 0, 1 -> CSINC zreg, zreg, cc 105 106 ; CHECK-LABEL: name: csinc_t_0_f_1 107 ; CHECK: liveins: $w0, $w1 108 ; CHECK: %reg0:gpr32 = COPY $w0 109 ; CHECK: %reg1:gpr32 = COPY $w1 110 ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv 111 ; CHECK: %select:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv 112 ; CHECK: $w0 = COPY %select 113 ; CHECK: RET_ReallyLR implicit $w0 114 %reg0:gpr(s32) = COPY $w0 115 %reg1:gpr(s32) = COPY $w1 116 %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1 117 %cond:gpr(s1) = G_TRUNC %cmp(s32) 118 %t:gpr(s32) = G_CONSTANT i32 0 119 %f:gpr(s32) = G_CONSTANT i32 1 120 %select:gpr(s32) = G_SELECT %cond(s1), %t, %f 121 $w0 = COPY %select(s32) 122 RET_ReallyLR implicit $w0 123... 124--- 125name: csinv_t_0_f_neg_1 126legalized: true 127regBankSelected: true 128tracksRegLiveness: true 129body: | 130 bb.0: 131 liveins: $w0, $w1 132 ; G_SELECT cc 0, -1 -> CSINV zreg, zreg cc 133 134 ; CHECK-LABEL: name: csinv_t_0_f_neg_1 135 ; CHECK: liveins: $w0, $w1 136 ; CHECK: %reg0:gpr32 = COPY $w0 137 ; CHECK: %reg1:gpr32 = COPY $w1 138 ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv 139 ; CHECK: %select:gpr32 = CSINVWr $wzr, $wzr, 1, implicit $nzcv 140 ; CHECK: $w0 = COPY %select 141 ; CHECK: RET_ReallyLR implicit $w0 142 %reg0:gpr(s32) = COPY $w0 143 %reg1:gpr(s32) = COPY $w1 144 %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1 145 %cond:gpr(s1) = G_TRUNC %cmp(s32) 146 %t:gpr(s32) = G_CONSTANT i32 0 147 %f:gpr(s32) = G_CONSTANT i32 -1 148 %select:gpr(s32) = G_SELECT %cond(s1), %t, %f 149 $w0 = COPY %select(s32) 150 RET_ReallyLR implicit $w0 151... 152--- 153name: csinc_t_1 154legalized: true 155regBankSelected: true 156tracksRegLiveness: true 157body: | 158 bb.0: 159 liveins: $w0, $w1, $w2 160 ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc 161 162 ; CHECK-LABEL: name: csinc_t_1 163 ; CHECK: liveins: $w0, $w1, $w2 164 ; CHECK: %reg0:gpr32 = COPY $w0 165 ; CHECK: %reg1:gpr32 = COPY $w1 166 ; CHECK: %f:gpr32 = COPY $w2 167 ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv 168 ; CHECK: %select:gpr32 = CSINCWr %f, $wzr, 0, implicit $nzcv 169 ; CHECK: $w0 = COPY %select 170 ; CHECK: RET_ReallyLR implicit $w0 171 %reg0:gpr(s32) = COPY $w0 172 %reg1:gpr(s32) = COPY $w1 173 %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1 174 %cond:gpr(s1) = G_TRUNC %cmp(s32) 175 %t:gpr(s32) = G_CONSTANT i32 1 176 %f:gpr(s32) = COPY $w2 177 %select:gpr(s32) = G_SELECT %cond(s1), %t, %f 178 $w0 = COPY %select(s32) 179 RET_ReallyLR implicit $w0 180... 181--- 182name: csinv_t_neg_1 183legalized: true 184regBankSelected: true 185tracksRegLiveness: true 186body: | 187 bb.0: 188 liveins: $w0, $w1, $w2 189 ; G_SELECT cc, -1, f -> CSINV f, zreg, inv_cc 190 191 ; CHECK-LABEL: name: csinv_t_neg_1 192 ; CHECK: liveins: $w0, $w1, $w2 193 ; CHECK: %reg0:gpr32 = COPY $w0 194 ; CHECK: %reg1:gpr32 = COPY $w1 195 ; CHECK: %f:gpr32 = COPY $w2 196 ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv 197 ; CHECK: %select:gpr32 = CSINVWr %f, $wzr, 0, implicit $nzcv 198 ; CHECK: $w0 = COPY %select 199 ; CHECK: RET_ReallyLR implicit $w0 200 %reg0:gpr(s32) = COPY $w0 201 %reg1:gpr(s32) = COPY $w1 202 %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1 203 %cond:gpr(s1) = G_TRUNC %cmp(s32) 204 %t:gpr(s32) = G_CONSTANT i32 -1 205 %f:gpr(s32) = COPY $w2 206 %select:gpr(s32) = G_SELECT %cond(s1), %t, %f 207 $w0 = COPY %select(s32) 208 RET_ReallyLR implicit $w0 209... 210--- 211name: csinc_f_1 212legalized: true 213regBankSelected: true 214tracksRegLiveness: true 215body: | 216 bb.0: 217 liveins: $w0, $w1, $w2 218 ; G_SELECT cc, t, 1 -> CSINC t, zreg, cc 219 220 ; CHECK-LABEL: name: csinc_f_1 221 ; CHECK: liveins: $w0, $w1, $w2 222 ; CHECK: %reg0:gpr32 = COPY $w0 223 ; CHECK: %reg1:gpr32 = COPY $w1 224 ; CHECK: %t:gpr32 = COPY $w2 225 ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv 226 ; CHECK: %select:gpr32 = CSINCWr %t, $wzr, 1, implicit $nzcv 227 ; CHECK: $w0 = COPY %select 228 ; CHECK: RET_ReallyLR implicit $w0 229 %reg0:gpr(s32) = COPY $w0 230 %reg1:gpr(s32) = COPY $w1 231 %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1 232 %cond:gpr(s1) = G_TRUNC %cmp(s32) 233 %t:gpr(s32) = COPY $w2 234 %f:gpr(s32) = G_CONSTANT i32 1 235 %select:gpr(s32) = G_SELECT %cond(s1), %t, %f 236 $w0 = COPY %select(s32) 237 RET_ReallyLR implicit $w0 238... 239--- 240name: csinc_f_neg_1 241legalized: true 242regBankSelected: true 243tracksRegLiveness: true 244body: | 245 bb.0: 246 liveins: $w0, $w1, $w2 247 ; G_SELECT cc, t, -1 -> CSINC t, zreg, cc 248 249 ; CHECK-LABEL: name: csinc_f_neg_1 250 ; CHECK: liveins: $w0, $w1, $w2 251 ; CHECK: %reg0:gpr32 = COPY $w0 252 ; CHECK: %reg1:gpr32 = COPY $w1 253 ; CHECK: %t:gpr32 = COPY $w2 254 ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %reg1, implicit-def $nzcv 255 ; CHECK: %select:gpr32 = CSINVWr %t, $wzr, 1, implicit $nzcv 256 ; CHECK: $w0 = COPY %select 257 ; CHECK: RET_ReallyLR implicit $w0 258 %reg0:gpr(s32) = COPY $w0 259 %reg1:gpr(s32) = COPY $w1 260 %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %reg1 261 %cond:gpr(s1) = G_TRUNC %cmp(s32) 262 %t:gpr(s32) = COPY $w2 263 %f:gpr(s32) = G_CONSTANT i32 -1 264 %select:gpr(s32) = G_SELECT %cond(s1), %t, %f 265 $w0 = COPY %select(s32) 266 RET_ReallyLR implicit $w0 267... 268--- 269name: csinc_t_1_no_cmp 270legalized: true 271regBankSelected: true 272tracksRegLiveness: true 273body: | 274 bb.0: 275 liveins: $w0, $w1 276 ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc 277 278 ; CHECK-LABEL: name: csinc_t_1_no_cmp 279 ; CHECK: liveins: $w0, $w1 280 ; CHECK: %reg0:gpr32 = COPY $w0 281 ; CHECK: %f:gpr32 = COPY $w1 282 ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv 283 ; CHECK: %select:gpr32 = CSINCWr %f, $wzr, 0, implicit $nzcv 284 ; CHECK: $w0 = COPY %select 285 ; CHECK: RET_ReallyLR implicit $w0 286 %reg0:gpr(s32) = COPY $w0 287 %cond:gpr(s1) = G_TRUNC %reg0(s32) 288 %t:gpr(s32) = G_CONSTANT i32 1 289 %f:gpr(s32) = COPY $w1 290 %select:gpr(s32) = G_SELECT %cond(s1), %t, %f 291 $w0 = COPY %select(s32) 292 RET_ReallyLR implicit $w0 293 294... 295--- 296name: csinc_f_1_no_cmp 297legalized: true 298regBankSelected: true 299tracksRegLiveness: true 300body: | 301 bb.0: 302 liveins: $w0, $w1 303 ; G_SELECT cc, t, 1 -> CSINC t, zreg, cc 304 305 ; CHECK-LABEL: name: csinc_f_1_no_cmp 306 ; CHECK: liveins: $w0, $w1 307 ; CHECK: %reg0:gpr32 = COPY $w0 308 ; CHECK: %t:gpr32 = COPY $w1 309 ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv 310 ; CHECK: %select:gpr32 = CSINCWr %t, $wzr, 1, implicit $nzcv 311 ; CHECK: $w0 = COPY %select 312 ; CHECK: RET_ReallyLR implicit $w0 313 %reg0:gpr(s32) = COPY $w0 314 %cond:gpr(s1) = G_TRUNC %reg0(s32) 315 %t:gpr(s32) = COPY $w1 316 %f:gpr(s32) = G_CONSTANT i32 1 317 %select:gpr(s32) = G_SELECT %cond(s1), %t, %f 318 $w0 = COPY %select(s32) 319 RET_ReallyLR implicit $w0 320 321... 322--- 323name: csinc_t_1_no_cmp_s64 324legalized: true 325regBankSelected: true 326tracksRegLiveness: true 327body: | 328 bb.0: 329 liveins: $x0, $x1 330 ; G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc 331 332 ; CHECK-LABEL: name: csinc_t_1_no_cmp_s64 333 ; CHECK: liveins: $x0, $x1 334 ; CHECK: %reg0:gpr64 = COPY $x0 335 ; CHECK: %cond:gpr32 = COPY %reg0.sub_32 336 ; CHECK: %f:gpr64 = COPY $x1 337 ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv 338 ; CHECK: %select:gpr64 = CSINCXr %f, $xzr, 0, implicit $nzcv 339 ; CHECK: $x0 = COPY %select 340 ; CHECK: RET_ReallyLR implicit $x0 341 %reg0:gpr(s64) = COPY $x0 342 %cond:gpr(s1) = G_TRUNC %reg0(s64) 343 %t:gpr(s64) = G_CONSTANT i64 1 344 %f:gpr(s64) = COPY $x1 345 %select:gpr(s64) = G_SELECT %cond(s1), %t, %f 346 $x0 = COPY %select(s64) 347 RET_ReallyLR implicit $x0 348 349... 350--- 351name: csneg_s32 352legalized: true 353regBankSelected: true 354tracksRegLiveness: true 355body: | 356 bb.0: 357 liveins: $w0, $w1, $w2 358 ; G_SELECT cc, true, (G_SUB 0, x) -> CSNEG true, x, cc 359 360 ; CHECK-LABEL: name: csneg_s32 361 ; CHECK: liveins: $w0, $w1, $w2 362 ; CHECK: %reg0:gpr32 = COPY $w0 363 ; CHECK: %reg1:gpr32 = COPY $w1 364 ; CHECK: %t:gpr32 = COPY $w2 365 ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv 366 ; CHECK: %select:gpr32 = CSNEGWr %t, %reg1, 1, implicit $nzcv 367 ; CHECK: $w0 = COPY %select 368 ; CHECK: RET_ReallyLR implicit $w0 369 %reg0:gpr(s32) = COPY $w0 370 %cond:gpr(s1) = G_TRUNC %reg0(s32) 371 %reg1:gpr(s32) = COPY $w1 372 %t:gpr(s32) = COPY $w2 373 %zero:gpr(s32) = G_CONSTANT i32 0 374 %sub:gpr(s32) = G_SUB %zero(s32), %reg1 375 %select:gpr(s32) = G_SELECT %cond(s1), %t, %sub 376 $w0 = COPY %select(s32) 377 RET_ReallyLR implicit $w0 378 379... 380--- 381name: csneg_inverted_cc 382legalized: true 383regBankSelected: true 384tracksRegLiveness: true 385body: | 386 bb.0: 387 liveins: $w0, $w1, $w2 388 ; G_SELECT cc, (G_SUB 0, %x), %false -> CSNEG %x, %false, inv_cc 389 390 ; CHECK-LABEL: name: csneg_inverted_cc 391 ; CHECK: liveins: $w0, $w1, $w2 392 ; CHECK: %reg0:gpr32 = COPY $w0 393 ; CHECK: %reg1:gpr32 = COPY $w1 394 ; CHECK: %f:gpr32 = COPY $w2 395 ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv 396 ; CHECK: %select:gpr32 = CSNEGWr %f, %reg1, 0, implicit $nzcv 397 ; CHECK: $w0 = COPY %select 398 ; CHECK: RET_ReallyLR implicit $w0 399 %reg0:gpr(s32) = COPY $w0 400 %cond:gpr(s1) = G_TRUNC %reg0(s32) 401 %reg1:gpr(s32) = COPY $w1 402 %f:gpr(s32) = COPY $w2 403 %zero:gpr(s32) = G_CONSTANT i32 0 404 %sub:gpr(s32) = G_SUB %zero(s32), %reg1 405 %select:gpr(s32) = G_SELECT %cond(s1), %sub, %f 406 $w0 = COPY %select(s32) 407 RET_ReallyLR implicit $w0 408 409... 410--- 411name: csneg_s64 412legalized: true 413regBankSelected: true 414tracksRegLiveness: true 415body: | 416 bb.0: 417 liveins: $x0, $x1, $x2 418 ; G_SELECT cc, true, (G_SUB 0, x) -> CSNEG true, x, cc 419 420 ; CHECK-LABEL: name: csneg_s64 421 ; CHECK: liveins: $x0, $x1, $x2 422 ; CHECK: %reg0:gpr64 = COPY $x0 423 ; CHECK: %cond:gpr32 = COPY %reg0.sub_32 424 ; CHECK: %reg1:gpr64 = COPY $x1 425 ; CHECK: %t:gpr64 = COPY $x2 426 ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv 427 ; CHECK: %select:gpr64 = CSNEGXr %t, %reg1, 1, implicit $nzcv 428 ; CHECK: $x0 = COPY %select 429 ; CHECK: RET_ReallyLR implicit $x0 430 %reg0:gpr(s64) = COPY $x0 431 %cond:gpr(s1) = G_TRUNC %reg0(s64) 432 %reg1:gpr(s64) = COPY $x1 433 %t:gpr(s64) = COPY $x2 434 %zero:gpr(s64) = G_CONSTANT i64 0 435 %sub:gpr(s64) = G_SUB %zero(s64), %reg1 436 %select:gpr(s64) = G_SELECT %cond(s1), %t, %sub 437 $x0 = COPY %select(s64) 438 RET_ReallyLR implicit $x0 439... 440--- 441name: csneg_with_true_cst 442legalized: true 443regBankSelected: true 444tracksRegLiveness: true 445body: | 446 bb.0: 447 liveins: $w0, $w1, $w2 448 ; We should prefer eliminating the G_SUB over eliminating the constant true 449 ; value. 450 451 ; CHECK-LABEL: name: csneg_with_true_cst 452 ; CHECK: liveins: $w0, $w1, $w2 453 ; CHECK: %reg0:gpr32 = COPY $w0 454 ; CHECK: %t:gpr32 = MOVi32imm 1 455 ; CHECK: %reg2:gpr32 = COPY $w2 456 ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv 457 ; CHECK: %select:gpr32 = CSNEGWr %t, %reg2, 1, implicit $nzcv 458 ; CHECK: $w0 = COPY %select 459 ; CHECK: RET_ReallyLR implicit $w0 460 %reg0:gpr(s32) = COPY $w0 461 %cond:gpr(s1) = G_TRUNC %reg0(s32) 462 %reg1:gpr(s32) = COPY $w1 463 %t:gpr(s32) = G_CONSTANT i32 1 464 %zero:gpr(s32) = G_CONSTANT i32 0 465 %reg2:gpr(s32) = COPY $w2 466 %sub:gpr(s32) = G_SUB %zero(s32), %reg2 467 %select:gpr(s32) = G_SELECT %cond(s1), %t, %sub 468 $w0 = COPY %select(s32) 469 RET_ReallyLR implicit $w0 470... 471--- 472name: csinv_s32 473legalized: true 474regBankSelected: true 475tracksRegLiveness: true 476body: | 477 bb.0: 478 liveins: $w0, $w1, $w2 479 ; G_SELECT cc, true, (G_XOR x, -1) -> CSINV true, x, cc 480 481 ; CHECK-LABEL: name: csinv_s32 482 ; CHECK: liveins: $w0, $w1, $w2 483 ; CHECK: %reg0:gpr32 = COPY $w0 484 ; CHECK: %reg1:gpr32 = COPY $w1 485 ; CHECK: %t:gpr32 = COPY $w2 486 ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv 487 ; CHECK: %select:gpr32 = CSINVWr %t, %reg1, 1, implicit $nzcv 488 ; CHECK: $w0 = COPY %select 489 ; CHECK: RET_ReallyLR implicit $w0 490 %reg0:gpr(s32) = COPY $w0 491 %reg1:gpr(s32) = COPY $w1 492 %cond:gpr(s1) = G_TRUNC %reg0(s32) 493 %t:gpr(s32) = COPY $w2 494 %negative_one:gpr(s32) = G_CONSTANT i32 -1 495 %xor:gpr(s32) = G_XOR %reg1(s32), %negative_one 496 %select:gpr(s32) = G_SELECT %cond(s1), %t, %xor 497 $w0 = COPY %select(s32) 498 RET_ReallyLR implicit $w0 499 500... 501--- 502name: csinv_inverted_cc 503legalized: true 504regBankSelected: true 505tracksRegLiveness: true 506body: | 507 bb.0: 508 liveins: $w0, $w1, $w2 509 ; G_SELECT cc, (G_XOR x, -1), %false -> CSINV %x, %false, inv_cc 510 511 ; CHECK-LABEL: name: csinv_inverted_cc 512 ; CHECK: liveins: $w0, $w1, $w2 513 ; CHECK: %reg0:gpr32 = COPY $w0 514 ; CHECK: %reg1:gpr32 = COPY $w1 515 ; CHECK: %f:gpr32 = COPY $w2 516 ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv 517 ; CHECK: %select:gpr32 = CSINVWr %f, %reg1, 0, implicit $nzcv 518 ; CHECK: $w0 = COPY %select 519 ; CHECK: RET_ReallyLR implicit $w0 520 %reg0:gpr(s32) = COPY $w0 521 %reg1:gpr(s32) = COPY $w1 522 %cond:gpr(s1) = G_TRUNC %reg0(s32) 523 %f:gpr(s32) = COPY $w2 524 %negative_one:gpr(s32) = G_CONSTANT i32 -1 525 %xor:gpr(s32) = G_XOR %reg1(s32), %negative_one 526 %select:gpr(s32) = G_SELECT %cond(s1), %xor, %f 527 $w0 = COPY %select(s32) 528 RET_ReallyLR implicit $w0 529 530... 531--- 532name: csinv_s64 533legalized: true 534regBankSelected: true 535tracksRegLiveness: true 536body: | 537 bb.0: 538 liveins: $x0, $x1, $x2 539 ; G_SELECT cc, true, (G_XOR x, -1) -> CSINV true, x, cc 540 541 ; CHECK-LABEL: name: csinv_s64 542 ; CHECK: liveins: $x0, $x1, $x2 543 ; CHECK: %reg0:gpr64 = COPY $x0 544 ; CHECK: %reg1:gpr64 = COPY $x1 545 ; CHECK: %cond:gpr32 = COPY %reg0.sub_32 546 ; CHECK: %t:gpr64 = COPY $x2 547 ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv 548 ; CHECK: %select:gpr64 = CSINVXr %t, %reg1, 1, implicit $nzcv 549 ; CHECK: $x0 = COPY %select 550 ; CHECK: RET_ReallyLR implicit $x0 551 %reg0:gpr(s64) = COPY $x0 552 %reg1:gpr(s64) = COPY $x1 553 %cond:gpr(s1) = G_TRUNC %reg0(s64) 554 %t:gpr(s64) = COPY $x2 555 %negative_one:gpr(s64) = G_CONSTANT i64 -1 556 %xor:gpr(s64) = G_XOR %reg1(s64), %negative_one 557 %select:gpr(s64) = G_SELECT %cond(s1), %t, %xor 558 $x0 = COPY %select(s64) 559 RET_ReallyLR implicit $x0 560 561... 562--- 563name: xor_not_negative_one 564legalized: true 565regBankSelected: true 566tracksRegLiveness: true 567body: | 568 bb.0: 569 liveins: $x0, $x1, $x2 570 ; zext(s32 -1) != s64 -1, so we can't fold it away. 571 572 ; CHECK-LABEL: name: xor_not_negative_one 573 ; CHECK: liveins: $x0, $x1, $x2 574 ; CHECK: %reg0:gpr64 = COPY $x0 575 ; CHECK: %reg1:gpr64 = COPY $x1 576 ; CHECK: %cond:gpr32 = COPY %reg0.sub_32 577 ; CHECK: %t:gpr64 = COPY $x2 578 ; CHECK: %negative_one:gpr32 = MOVi32imm -1 579 ; CHECK: %zext:gpr64 = SUBREG_TO_REG 0, %negative_one, %subreg.sub_32 580 ; CHECK: %xor:gpr64 = EORXrr %reg1, %zext 581 ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %cond, 0, implicit-def $nzcv 582 ; CHECK: %select:gpr64 = CSELXr %t, %xor, 1, implicit $nzcv 583 ; CHECK: $x0 = COPY %select 584 ; CHECK: RET_ReallyLR implicit $x0 585 %reg0:gpr(s64) = COPY $x0 586 %reg1:gpr(s64) = COPY $x1 587 %cond:gpr(s1) = G_TRUNC %reg0(s64) 588 %t:gpr(s64) = COPY $x2 589 %negative_one:gpr(s32) = G_CONSTANT i32 -1 590 %zext:gpr(s64) = G_ZEXT %negative_one(s32) 591 %xor:gpr(s64) = G_XOR %reg1(s64), %zext 592 %select:gpr(s64) = G_SELECT %cond(s1), %t, %xor 593 $x0 = COPY %select(s64) 594 RET_ReallyLR implicit $x0 595 596... 597--- 598name: csinc_s32 599legalized: true 600regBankSelected: true 601tracksRegLiveness: true 602body: | 603 bb.0: 604 liveins: $w0, $w1, $w2 605 ; G_SELECT cc, %true, (G_ADD %x, 1) -> CSINC %true, %x, cc 606 ; CHECK-LABEL: name: csinc_s32 607 ; CHECK: liveins: $w0, $w1, $w2 608 ; CHECK: %reg0:gpr32 = COPY $w0 609 ; CHECK: %reg1:gpr32 = COPY $w1 610 ; CHECK: %t:gpr32 = COPY $w2 611 ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv 612 ; CHECK: %select:gpr32 = CSINCWr %t, %reg1, 1, implicit $nzcv 613 ; CHECK: $w0 = COPY %select 614 ; CHECK: RET_ReallyLR implicit $w0 615 %reg0:gpr(s32) = COPY $w0 616 %reg1:gpr(s32) = COPY $w1 617 %cond:gpr(s1) = G_TRUNC %reg0(s32) 618 %t:gpr(s32) = COPY $w2 619 %one:gpr(s32) = G_CONSTANT i32 1 620 %add:gpr(s32) = G_ADD %reg1(s32), %one 621 %select:gpr(s32) = G_SELECT %cond(s1), %t, %add 622 $w0 = COPY %select(s32) 623 RET_ReallyLR implicit $w0 624 625... 626--- 627name: csinc_s32_inverted_cc 628legalized: true 629regBankSelected: true 630tracksRegLiveness: true 631body: | 632 bb.0: 633 liveins: $w0, $w1, $w2 634 ; G_SELECT cc, (G_ADD %x, 1), %false -> CSINC %x, %false, inv_cc 635 ; CHECK-LABEL: name: csinc_s32_inverted_cc 636 ; CHECK: liveins: $w0, $w1, $w2 637 ; CHECK: %reg0:gpr32 = COPY $w0 638 ; CHECK: %reg1:gpr32 = COPY $w1 639 ; CHECK: %f:gpr32 = COPY $w2 640 ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv 641 ; CHECK: %select:gpr32 = CSINCWr %f, %reg1, 0, implicit $nzcv 642 ; CHECK: $w0 = COPY %select 643 ; CHECK: RET_ReallyLR implicit $w0 644 %reg0:gpr(s32) = COPY $w0 645 %reg1:gpr(s32) = COPY $w1 646 %cond:gpr(s1) = G_TRUNC %reg0(s32) 647 %f:gpr(s32) = COPY $w2 648 %one:gpr(s32) = G_CONSTANT i32 1 649 %add:gpr(s32) = G_ADD %reg1(s32), %one 650 %select:gpr(s32) = G_SELECT %cond(s1), %add, %f 651 $w0 = COPY %select(s32) 652 RET_ReallyLR implicit $w0 653 654... 655--- 656name: binop_dont_optimize_twice 657legalized: true 658regBankSelected: true 659tracksRegLiveness: true 660body: | 661 bb.0: 662 liveins: $w0, $w1, $w2 663 ; CHECK-LABEL: name: binop_dont_optimize_twice 664 ; CHECK: liveins: $w0, $w1, $w2 665 ; CHECK: %reg0:gpr32 = COPY $w0 666 ; CHECK: %reg1:gpr32 = COPY $w1 667 ; CHECK: %reg2:gpr32 = COPY $w2 668 ; CHECK: %xor:gpr32 = ORNWrr $wzr, %reg1 669 ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv 670 ; CHECK: %select:gpr32 = CSNEGWr %xor, %reg2, 1, implicit $nzcv 671 ; CHECK: $w0 = COPY %select 672 ; CHECK: RET_ReallyLR implicit $w0 673 %reg0:gpr(s32) = COPY $w0 674 %reg1:gpr(s32) = COPY $w1 675 %reg2:gpr(s32) = COPY $w2 676 %cond:gpr(s1) = G_TRUNC %reg0(s32) 677 %f:gpr(s32) = COPY $w2 678 %negative_one:gpr(s32) = G_CONSTANT i32 -1 679 %xor:gpr(s32) = G_XOR %reg1(s32), %negative_one 680 %zero:gpr(s32) = G_CONSTANT i32 0 681 %sub:gpr(s32) = G_SUB %zero(s32), %reg2 682 %select:gpr(s32) = G_SELECT %cond(s1), %xor, %sub 683 $w0 = COPY %select(s32) 684 RET_ReallyLR implicit $w0 685