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Searched refs:zero_reg (Results 1 – 25 of 29) sorted by relevance

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/external/libaom/libaom/aom_dsp/x86/
Dvariance_impl_avx2.c72 exp_dst_lo = _mm256_unpacklo_epi8(dst_reg, zero_reg); \
73 exp_dst_hi = _mm256_unpackhi_epi8(dst_reg, zero_reg); \
88 res_cmp = _mm256_cmpgt_epi16(zero_reg, sum_reg); \
172 __m256i zero_reg; in aom_sub_pixel_variance32xh_avx2() local
176 zero_reg = _mm256_set1_epi16(0); in aom_sub_pixel_variance32xh_avx2()
184 MERGE_WITH_SRC(src_reg, zero_reg) in aom_sub_pixel_variance32xh_avx2()
196 MERGE_WITH_SRC(src_reg, zero_reg) in aom_sub_pixel_variance32xh_avx2()
226 MERGE_WITH_SRC(src_reg, zero_reg) in aom_sub_pixel_variance32xh_avx2()
246 MERGE_WITH_SRC(src_avg, zero_reg) in aom_sub_pixel_variance32xh_avx2()
310 MERGE_WITH_SRC(src_pack, zero_reg) in aom_sub_pixel_variance32xh_avx2()
[all …]
/external/libvpx/libvpx/vpx_dsp/x86/
Dvariance_avx2.c190 exp_dst_lo = _mm256_unpacklo_epi8(dst_reg, zero_reg); \
191 exp_dst_hi = _mm256_unpackhi_epi8(dst_reg, zero_reg); \
206 res_cmp = _mm256_cmpgt_epi16(zero_reg, sum_reg); \
230 const __m256i zero_reg = _mm256_setzero_si256(); in spv32_x0_y0() local
239 exp_src_lo = _mm256_unpacklo_epi8(avg_reg, zero_reg); in spv32_x0_y0()
240 exp_src_hi = _mm256_unpackhi_epi8(avg_reg, zero_reg); in spv32_x0_y0()
243 exp_src_lo = _mm256_unpacklo_epi8(src_reg, zero_reg); in spv32_x0_y0()
244 exp_src_hi = _mm256_unpackhi_epi8(src_reg, zero_reg); in spv32_x0_y0()
259 const __m256i zero_reg = _mm256_setzero_si256(); in spv32_half_zero() local
270 exp_src_lo = _mm256_unpacklo_epi8(avg_reg, zero_reg); in spv32_half_zero()
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc84 /* 54*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
92 /* 72*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
122 /* 129*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
130 /* 147*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
157 /* 200*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
183 /* 255*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
202 /* 294*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
229 /* 349*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
256 /* 407*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
275 /* 446*/ OPC_EmitRegister, MVT::i32, 0 /*zero_reg*/,
[all …]
DARMGenGlobalISel.inc926 GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
950 GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
974 GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
998 GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1022 GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1046 GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1070 GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1094 GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1130 GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
1166 GIR_AddRegister, /*InsnID*/0, ::zero_reg, /*AddRegisterRegFlags*/0,
[all …]
/external/libaom/libaom/av1/encoder/x86/
Derror_intrin_avx2.c93 const __m256i zero_reg = _mm256_setzero_si256(); in av1_block_error_avx2() local
110 exp_dqcoeff_lo = _mm256_unpacklo_epi32(dqcoeff_reg, zero_reg); in av1_block_error_avx2()
111 exp_dqcoeff_hi = _mm256_unpackhi_epi32(dqcoeff_reg, zero_reg); in av1_block_error_avx2()
113 exp_coeff_lo = _mm256_unpacklo_epi32(coeff_reg, zero_reg); in av1_block_error_avx2()
114 exp_coeff_hi = _mm256_unpackhi_epi32(coeff_reg, zero_reg); in av1_block_error_avx2()
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoVPseudos.td181 (mask_type zero_reg),
269 (mask_type zero_reg),
274 (mask_type zero_reg),
280 (mask_type zero_reg),
284 (mask_type zero_reg),
/external/llvm-project/llvm/test/TableGen/
DGlobalISelEmitter-zero-reg.td12 (ops (i32 zero_reg))> {}
/external/llvm/include/llvm/Target/
DTarget.td697 /// zero_reg definition - Special node to stand for the zero register.
699 def zero_reg;
727 /// none is supplied, e.g. zero_reg.
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp167 const unsigned zero_reg = 0; variable
DARMInstrFormats.td158 (ops (i32 14), (i32 zero_reg))> {
176 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
225 // always either zero_reg or VPR, but needs to be modelled as an
253 !con((ops (i32 0), (i32 zero_reg)), extra_op)> {
DARMInstrInfo.td2442 (ops 14, zero_reg))>,
2504 (Bcc arm_br_target:$dst, (ops 14, zero_reg))>,
5747 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5753 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
6175 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
DARMInstrThumb2.td2068 pred:$p, zero_reg)>;
2095 pred:$p, zero_reg)>;
2097 pred:$p, zero_reg)>;
5055 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
DARMInstrThumb.td628 (tBX GPR:$dst, (ops 14, zero_reg))>,
/external/vixl/src/aarch64/
Dlogic-aarch64.cc4991 LogicVRegister zero_reg = in fcmp_zero() local
4993 fcmp<SimFloat16>(vform, dst, src, zero_reg, cond); in fcmp_zero()
4995 LogicVRegister zero_reg = dup_immediate(vform, temp, FloatToRawbits(0.0)); in fcmp_zero() local
4996 fcmp<float>(vform, dst, src, zero_reg, cond); in fcmp_zero()
4999 LogicVRegister zero_reg = dup_immediate(vform, temp, DoubleToRawbits(0.0)); in fcmp_zero() local
5000 fcmp<double>(vform, dst, src, zero_reg, cond); in fcmp_zero()
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrFormats.td158 (ops (i32 14), (i32 zero_reg))> {
176 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
224 // always either zero_reg or VPR, but needs to be modelled as an
252 !con((ops (i32 0), (i32 zero_reg)), extra_op)> {
DARMInstrInfo.td2557 (ops 14, zero_reg))>,
2619 (Bcc arm_br_target:$dst, (ops 14, zero_reg))>,
5898 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5904 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
6332 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
DARMInstrThumb2.td2117 pred:$p, zero_reg)>;
2144 pred:$p, zero_reg)>;
2146 pred:$p, zero_reg)>;
5130 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
DARMInstrThumb.td640 (tBX GPR:$dst, (ops 14, zero_reg))>,
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTarget.td887 /// zero_reg definition - Special node to stand for the zero register.
889 def zero_reg;
917 /// none is supplied, e.g. zero_reg.
/external/llvm-project/llvm/include/llvm/Target/
DTarget.td906 /// zero_reg definition - Special node to stand for the zero register.
908 def zero_reg;
940 /// none is supplied, e.g. zero_reg.
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td1873 pred:$p, zero_reg)>;
1900 pred:$p, zero_reg)>;
1902 pred:$p, zero_reg)>;
4736 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
4738 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
DARMInstrInfo.td2288 (ops 14, zero_reg))>,
2347 (Bcc arm_br_target:$dst, (ops 14, zero_reg))>,
5385 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5777 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
DARMInstrFormats.td152 (ops (i32 14), (i32 zero_reg))> {
170 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
DARMInstrThumb.td591 (tBX GPR:$dst, (ops 14, zero_reg))>,
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.td2086 zero_reg, 1)>;

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