| /external/llvm/lib/CodeGen/ |
| D | RegUsageInfoCollector.cpp | 80 uint32_t *RegMask, unsigned PReg) { in markRegClobbered()
117 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) in runOnMachineFunction() local
133 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) in runOnMachineFunction() local
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| D | RegisterUsageInfo.cpp | 86 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { in print() local
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| D | RegAllocPBQP.cpp | 587 unsigned PReg = RawPRegOrder[I]; in initializeGraph() local
685 unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1]; in mapPBQPToRegAlloc() local
713 unsigned PReg = MRI.getSimpleHint(LI.reg); in finalizeAlloc() local
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| D | CallingConvLower.cpp | 246 for (MCPhysReg PReg : RemainingRegs) { in analyzeMustTailForwardedRegisters() local
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| D | MachineFunction.cpp | 512 unsigned MachineFunction::addLiveIn(unsigned PReg, in addLiveIn()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ExpandSpecialInstrs.cpp | 122 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister( in runOnMachineFunction() local
151 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister( in runOnMachineFunction() local
181 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister( in runOnMachineFunction() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyReplacePhysRegs.cpp | 79 for (unsigned PReg = WebAssembly::NoRegister + 1; in runOnMachineFunction() local
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyReplacePhysRegs.cpp | 76 for (unsigned PReg = WebAssembly::NoRegister + 1; in runOnMachineFunction() local
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| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyReplacePhysRegs.cpp | 79 for (unsigned PReg = WebAssembly::NoRegister + 1; in runOnMachineFunction() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RegisterUsageInfo.cpp | 95 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { in print() local
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| D | RegUsageInfoCollector.cpp | 155 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { in runOnMachineFunction() local
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| D | RegAllocPBQP.cpp | 614 unsigned PReg = RawPRegOrder[I]; in initializeGraph() local
725 unsigned PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOption - 1]; in mapPBQPToRegAlloc() local
753 unsigned PReg = MRI.getSimpleHint(LI.reg); in finalizeAlloc() local
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| D | CallingConvLower.cpp | 252 for (MCPhysReg PReg : RemainingRegs) { in analyzeMustTailForwardedRegisters() local
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | RegisterUsageInfo.cpp | 95 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { in print() local
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| D | RegUsageInfoCollector.cpp | 155 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { in runOnMachineFunction() local
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| D | RegAllocPBQP.cpp | 627 MCRegister PReg(RawPRegOrder[I]); in initializeGraph() local
739 MCRegister PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOpt - 1]; in mapPBQPToRegAlloc() local
767 Register PReg = MRI.getSimpleHint(LI.reg()); in finalizeAlloc() local
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| D | CallingConvLower.cpp | 259 for (MCPhysReg PReg : RemainingRegs) { in analyzeMustTailForwardedRegisters() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonBlockRanges.cpp | 272 unsigned PReg = *RC.begin(); in expandToSubRegs() local
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| D | HexagonBitTracker.cpp | 1130 unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const { in getNextPhysReg()
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 171 MCPhysReg PReg; member
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonBlockRanges.cpp | 280 unsigned PReg = *RC.begin(); in expandToSubRegs() local
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| D | HexagonBitTracker.cpp | 1247 unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const { in getNextPhysReg()
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| /external/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 169 MCPhysReg PReg; member
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonBlockRanges.cpp | 280 unsigned PReg = *RC.begin(); in expandToSubRegs() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | CallingConvLower.h | 171 MCPhysReg PReg; member
|