| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallingConv.cpp | 33 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, in CC_X86_32_RegCall_Assign2Regs() local
96 ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT); in CC_X86_VectorCallAssignRegister() local
242 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg() local
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86CallingConv.cpp | 33 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, in CC_X86_32_RegCall_Assign2Regs() local
96 ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT); in CC_X86_VectorCallAssignRegister() local
242 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg() local
|
| /external/llvm-project/llvm/utils/TableGen/ |
| D | CallingConvEmitter.cpp | 126 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
147 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.cpp | 24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS() local
197 ArrayRef<MCPhysReg> RegList; in CC_ARM_AAPCS_Custom_Aggregate() local
286 ArrayRef<MCPhysReg> RegList) { in CustomAssignInRegList()
|
| D | Thumb2ITBlockPass.cpp | 83 using RegList = SmallVector<unsigned, 4>; in INITIALIZE_PASS() typedef
|
| D | ARMBaseRegisterInfo.cpp | 70 const MCPhysReg *RegList = in getCalleeSavedRegs() local
|
| /external/llvm/utils/TableGen/ |
| D | CallingConvEmitter.cpp | 113 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
134 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.h | 31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS() local
206 ArrayRef<MCPhysReg> RegList; in CC_ARM_AAPCS_Custom_Aggregate() local
|
| D | ARMBaseRegisterInfo.cpp | 64 const MCPhysReg *RegList = in getCalleeSavedRegs() local
|
| D | ARMAsmPrinter.cpp | 1161 SmallVector<unsigned, 4> RegList; in EmitUnwindingInstruction() local
|
| /external/llvm/lib/Target/X86/ |
| D | X86CallingConv.h | 53 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.cpp | 24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS() local
199 ArrayRef<MCPhysReg> RegList; in CC_ARM_AAPCS_Custom_Aggregate() local
|
| D | Thumb2ITBlockPass.cpp | 83 using RegList = SmallVector<unsigned, 4>; in INITIALIZE_PASS() typedef
|
| D | ARMBaseRegisterInfo.cpp | 68 const MCPhysReg *RegList = in getCalleeSavedRegs() local
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.h | 89 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.cpp | 90 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block() local
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConvention.cpp | 137 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block() local
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMTargetStreamer.cpp | 56 void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
|
| D | ARMELFStreamer.cpp | 137 void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
649 void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
1328 void ARMELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
|
| /external/llvm/lib/CodeGen/ |
| D | MachineCopyPropagation.cpp | 35 typedef SmallVector<unsigned, 4> RegList; typedef
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMTargetStreamer.cpp | 98 void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
|
| D | ARMELFStreamer.cpp | 157 void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
749 void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
1452 void ARMELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
|
| /external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMTargetStreamer.cpp | 98 void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
|
| D | ARMELFStreamer.cpp | 157 void ARMTargetAsmStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
741 void ARMTargetELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
1445 void ARMELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave()
|
| /external/vixl/src/aarch64/ |
| D | registers-aarch64.h | 39 typedef uint64_t RegList; typedef
|