1 //=== AArch64CallingConvention.cpp - AArch64 CC impl ------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the table-generated and custom routines for the AArch64
10 // Calling Convention.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "AArch64CallingConvention.h"
15 #include "AArch64.h"
16 #include "AArch64InstrInfo.h"
17 #include "AArch64Subtarget.h"
18 #include "llvm/CodeGen/CallingConvLower.h"
19 #include "llvm/CodeGen/TargetInstrInfo.h"
20 #include "llvm/IR/CallingConv.h"
21 using namespace llvm;
22
23 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
24 AArch64::X3, AArch64::X4, AArch64::X5,
25 AArch64::X6, AArch64::X7};
26 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
27 AArch64::H3, AArch64::H4, AArch64::H5,
28 AArch64::H6, AArch64::H7};
29 static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
30 AArch64::S3, AArch64::S4, AArch64::S5,
31 AArch64::S6, AArch64::S7};
32 static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
33 AArch64::D3, AArch64::D4, AArch64::D5,
34 AArch64::D6, AArch64::D7};
35 static const MCPhysReg QRegList[] = {AArch64::Q0, AArch64::Q1, AArch64::Q2,
36 AArch64::Q3, AArch64::Q4, AArch64::Q5,
37 AArch64::Q6, AArch64::Q7};
38
finishStackBlock(SmallVectorImpl<CCValAssign> & PendingMembers,MVT LocVT,ISD::ArgFlagsTy & ArgFlags,CCState & State,unsigned SlotAlign)39 static bool finishStackBlock(SmallVectorImpl<CCValAssign> &PendingMembers,
40 MVT LocVT, ISD::ArgFlagsTy &ArgFlags,
41 CCState &State, unsigned SlotAlign) {
42 unsigned Size = LocVT.getSizeInBits() / 8;
43 const Align StackAlign =
44 State.getMachineFunction().getDataLayout().getStackAlignment();
45 const Align OrigAlign(ArgFlags.getOrigAlign());
46 const Align Align = std::min(OrigAlign, StackAlign);
47
48 for (auto &It : PendingMembers) {
49 It.convertToMem(State.AllocateStack(
50 Size, std::max((unsigned)Align.value(), SlotAlign)));
51 State.addLoc(It);
52 SlotAlign = 1;
53 }
54
55 // All pending members have now been allocated
56 PendingMembers.clear();
57 return true;
58 }
59
60 /// The Darwin variadic PCS places anonymous arguments in 8-byte stack slots. An
61 /// [N x Ty] type must still be contiguous in memory though.
CC_AArch64_Custom_Stack_Block(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)62 static bool CC_AArch64_Custom_Stack_Block(
63 unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo,
64 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
65 SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
66
67 // Add the argument to the list to be allocated once we know the size of the
68 // block.
69 PendingMembers.push_back(
70 CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
71
72 if (!ArgFlags.isInConsecutiveRegsLast())
73 return true;
74
75 return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, 8);
76 }
77
78 /// Given an [N x Ty] block, it should be passed in a consecutive sequence of
79 /// registers. If no such sequence is available, mark the rest of the registers
80 /// of that type as used and place the argument on the stack.
CC_AArch64_Custom_Block(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)81 static bool CC_AArch64_Custom_Block(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
82 CCValAssign::LocInfo &LocInfo,
83 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
84 const AArch64Subtarget &Subtarget = static_cast<const AArch64Subtarget &>(
85 State.getMachineFunction().getSubtarget());
86 bool IsDarwinILP32 = Subtarget.isTargetILP32() && Subtarget.isTargetMachO();
87
88 // Try to allocate a contiguous block of registers, each of the correct
89 // size to hold one member.
90 ArrayRef<MCPhysReg> RegList;
91 if (LocVT.SimpleTy == MVT::i64 || (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32))
92 RegList = XRegList;
93 else if (LocVT.SimpleTy == MVT::f16)
94 RegList = HRegList;
95 else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector())
96 RegList = SRegList;
97 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector())
98 RegList = DRegList;
99 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector())
100 RegList = QRegList;
101 else {
102 // Not an array we want to split up after all.
103 return false;
104 }
105
106 SmallVectorImpl<CCValAssign> &PendingMembers = State.getPendingLocs();
107
108 // Add the argument to the list to be allocated once we know the size of the
109 // block.
110 PendingMembers.push_back(
111 CCValAssign::getPending(ValNo, ValVT, LocVT, LocInfo));
112
113 if (!ArgFlags.isInConsecutiveRegsLast())
114 return true;
115
116 // [N x i32] arguments get packed into x-registers on Darwin's arm64_32
117 // because that's how the armv7k Clang front-end emits small structs.
118 unsigned EltsPerReg = (IsDarwinILP32 && LocVT.SimpleTy == MVT::i32) ? 2 : 1;
119 unsigned RegResult = State.AllocateRegBlock(
120 RegList, alignTo(PendingMembers.size(), EltsPerReg) / EltsPerReg);
121 if (RegResult && EltsPerReg == 1) {
122 for (auto &It : PendingMembers) {
123 It.convertToReg(RegResult);
124 State.addLoc(It);
125 ++RegResult;
126 }
127 PendingMembers.clear();
128 return true;
129 } else if (RegResult) {
130 assert(EltsPerReg == 2 && "unexpected ABI");
131 bool UseHigh = false;
132 CCValAssign::LocInfo Info;
133 for (auto &It : PendingMembers) {
134 Info = UseHigh ? CCValAssign::AExtUpper : CCValAssign::ZExt;
135 State.addLoc(CCValAssign::getReg(It.getValNo(), MVT::i32, RegResult,
136 MVT::i64, Info));
137 UseHigh = !UseHigh;
138 if (!UseHigh)
139 ++RegResult;
140 }
141 PendingMembers.clear();
142 return true;
143 }
144
145 // Mark all regs in the class as unavailable
146 for (auto Reg : RegList)
147 State.AllocateReg(Reg);
148
149 unsigned SlotAlign = Subtarget.isTargetDarwin() ? 1 : 8;
150
151 return finishStackBlock(PendingMembers, LocVT, ArgFlags, State, SlotAlign);
152 }
153
154 // TableGen provides definitions of the calling convention analysis entry
155 // points.
156 #include "AArch64GenCallingConv.inc"
157