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/external/llvm-project/llvm/test/CodeGen/Mips/
Dlongbranch.ll42 ; NOLONGBRANCH-NEXT: beqz $4, $BB0_2
48 ; NOLONGBRANCH-NEXT: $BB0_2: # %end
61 ; O32-PIC-NEXT: lui $1, %hi(($BB0_4)-($BB0_2))
62 ; O32-PIC-NEXT: bal $BB0_2
63 ; O32-PIC-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2))
64 ; O32-PIC-NEXT: $BB0_2: # %entry
79 ; O32-STATIC-NEXT: bnez $4, $BB0_2
84 ; O32-STATIC-NEXT: $BB0_2: # %then
101 ; O32-R6-PIC-NEXT: lui $1, %hi(($BB0_4)-($BB0_2))
102 ; O32-R6-PIC-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2))
[all …]
Dmicromips-mtc-mfc.ll14 ; MM2-NEXT: bc1t $BB0_2 # encoding: [0x43,0xa0,A,A]
15 ; MM2-NEXT: # fixup A - offset: 0, value: ($BB0_2), kind: fixup_MICROMIPS_PC16_S1
18 ; MM2-NEXT: j $BB0_2 # encoding: [0b110101AA,A,A,A]
19 ; MM2-NEXT: # fixup A - offset: 0, value: ($BB0_2), kind: fixup_MICROMIPS_26_S1
21 ; MM2-NEXT: $BB0_2: # %return
Dblez_bgez.ll11 ; MIPS32-NEXT: blez $4, $BB0_2
22 ; MIPS32-NEXT: $BB0_2: # %if.end
49 ; MM-NEXT: j $BB0_2
51 ; MM-NEXT: $BB0_2: # %if.then
/external/llvm/test/MC/Mips/
Dmips_directives.s4 # CHECK: $BB0_2:
6 $BB0_2:
29 .gpword ($BB0_2)
33 # CHECK: .gpword ($BB0_2)
53 .set $tmp7, $BB0_4-$BB0_2
Delf-gprel-32-64.s42 bnez $1, $BB0_2
47 $BB0_2: # %entry
Ddo_switch1.s31 bnez $1, $BB0_2
37 $BB0_2: # %entry
Ddo_switch2.s32 bnez $1, $BB0_2
38 $BB0_2: # %entry
Ddo_switch3.s33 bnez $4, $BB0_2
39 $BB0_2: # %entry
/external/llvm-project/llvm/test/MC/Mips/
Dmips_directives.s4 # CHECK: $BB0_2:
6 $BB0_2:
29 .gpword ($BB0_2)
33 # CHECK: .gpword ($BB0_2)
53 .set $tmp7, $BB0_4-$BB0_2
Delf-gprel-32-64.s42 bnez $1, $BB0_2
47 $BB0_2: # %entry
Ddo_switch1.s31 bnez $1, $BB0_2
37 $BB0_2: # %entry
Ddo_switch2.s32 bnez $1, $BB0_2
38 $BB0_2: # %entry
Ddo_switch3.s33 bnez $4, $BB0_2
39 $BB0_2: # %entry
/external/llvm-project/llvm/test/MC/AMDGPU/
Doffsetbug_twice.s4 s_cbranch_vccnz BB0_2
108 s_cbranch_vccnz BB0_2
115 BB0_2: label
/external/llvm-project/llvm/test/CodeGen/Mips/indirect-jump-hazard/
Dlong-branch.ll37 ; O32-PIC-NEXT: lui $1, %hi(($BB0_4)-($BB0_2))
38 ; O32-PIC-NEXT: bal $BB0_2
39 ; O32-PIC-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2))
40 ; O32-PIC-NEXT: $BB0_2: # %entry
62 ; O32-R6-PIC-NEXT: lui $1, %hi(($BB0_4)-($BB0_2))
63 ; O32-R6-PIC-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2))
64 ; O32-R6-PIC-NEXT: balc $BB0_2
65 ; O32-R6-PIC-NEXT: $BB0_2: # %entry
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Daix-lower-jump-table.ll98 ; 32SMALL-ASM: L..BB0_2:
108 ; 32SMALL-ASM: .vbyte 4, L..BB0_2-L..JTI0_0
125 ; 32LARGE-ASM: L..BB0_2:
135 ; 32LARGE-ASM: .vbyte 4, L..BB0_2-L..JTI0_0
151 ; 64SMALL-ASM: L..BB0_2:
161 ; 64SMALL-ASM: .vbyte 4, L..BB0_2-L..JTI0_0
178 ; 64LARGE-ASM: L..BB0_2:
188 ; 64LARGE-ASM: .vbyte 4, L..BB0_2-L..JTI0_0
194 ; FUNC-ASM: L..BB0_2:
204 ; FUNC-ASM: .vbyte 4, L..BB0_2-L..JTI0_0
/external/llvm-project/llvm/test/CodeGen/Thumb/
Dpr42760.ll11 ; CHECK-NEXT: @ in Loop: Header=BB0_2 Depth=1
27 ; CHECK-NEXT: @ in Loop: Header=BB0_2 Depth=1
30 ; CHECK-NEXT: @ in Loop: Header=BB0_2 Depth=1
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dvgpr-descriptor-waterfall-loop-idom-update.ll11 ; GCN-NEXT: ; Child Loop BB0_2 Depth 2
18 ; GCN-NEXT: BB0_2: ; Parent Loop BB0_1 Depth=1
33 ; GCN-NEXT: s_cbranch_execnz BB0_2
Dsi-annotate-cfg-loop-assert.ll16 ; CHECK-NEXT: BB0_2: ; %bb10
19 ; CHECK-NEXT: s_cbranch_vccz BB0_2
Dlds-m0-init-in-loop.ll11 ; GCN: BB0_2:
17 ; GCN: s_cbranch_scc0 BB0_2
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dllvm.amdgcn.end.cf.i64.ll14 ; GCN-NEXT: s_cbranch_scc1 BB0_2
18 ; GCN-NEXT: BB0_2: ; %bb
Dllvm.amdgcn.end.cf.i32.ll15 ; GCN-NEXT: s_cbranch_scc1 BB0_2
19 ; GCN-NEXT: BB0_2: ; %bb
/external/llvm/test/CodeGen/X86/
Dlsr-static-addr.ll7 ; CHECK-NEXT: BB0_2:
17 ; ATOM-NEXT: BB0_2:
/external/llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
Dsibling-loops.ll22 ; CHECK-NEXT: @ Parent Loop BB0_2 Depth=1
31 ; CHECK-NEXT: @ in Loop: Header=BB0_2 Depth=1
35 ; CHECK-NEXT: @ Parent Loop BB0_2 Depth=1
44 ; CHECK-NEXT: @ in Loop: Header=BB0_2 Depth=1
/external/llvm/test/CodeGen/AMDGPU/
Dlds-m0-init-in-loop.ll11 ; GCN: BB0_2:
15 ; GCN: s_cbranch_vccz BB0_2

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