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Searched refs:C12 (Results 1 – 25 of 99) sorted by relevance

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/external/llvm-project/mlir/test/Transforms/
Dparallel-loop-collapsing.mlir37 // CHECK: [[C12:%.*]] = constant 12 : index
43 // CHECK: "magic.op"([[I0]], [[C3]], [[C6]], [[I3]], [[C12]]) : (index, index, index, ind…
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Darm64-callingconv-ios.ll39 ; CHECK: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
40 ; CHECK: [[PTR_ADD4:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](s64)
78 ; CHECK: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
79 ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](s64)
Dcall-translator-ios.ll22 ; CHECK: [[C12:%[0-9]+]]:_(s8) = G_CONSTANT i8 12
29 ; CHECK: G_STORE [[C12]](s8), [[C12_LOC]](p0) :: (store 1 into stack + 1)
Darm64-callingconv.ll203 ; CHECK: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
204 ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](s64)
Dcall-translator.ll231 ; CHECK: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
240 ; CHECK: G_STORE [[C12]](s64), [[C12_LOC]](p0) :: (store 8 into stack + 8, align 1)
Dcombine-unmerge.mir208 ; CHECK: [[C12:%[0-9]+]]:_(s8) = G_CONSTANT i8 4
224 ; CHECK: $b12 = COPY [[C12]](s8)
/external/libvpx/libvpx/test/
Ddct16x16_test.cc47 const double C12 = 0.38268343236509; variable
153 temp1 = step[2] * C12; in butterfly_16x16_dct_1d()
159 temp2 = step[3] * C12; in butterfly_16x16_dct_1d()
174 temp1 = intermediate[8] * C12; in butterfly_16x16_dct_1d()
180 temp2 = intermediate[9] * C12; in butterfly_16x16_dct_1d()
197 temp1 = intermediate[14] * C12; in butterfly_16x16_dct_1d()
203 temp2 = intermediate[15] * C12; in butterfly_16x16_dct_1d()
/external/cldr/tools/java/org/unicode/cldr/draft/keyboard/windows/
Dwindows-keycodes.csv38 43,C12
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-fptrunc.mir122 ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
123 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]]
202 ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
203 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]]
253 ; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[C12]]
329 ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
330 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]]
409 ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 4096
410 ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[OR1]], [[C12]]
460 ; CHECK: [[OR12:%[0-9]+]]:_(s32) = G_OR [[OR9]], [[C12]]
Dregbankselect-extract-vector-elt.mir85 ; WAVE64: [[C12:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 13
86 ; WAVE64: [[ICMP12:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C12]]
137 ; WAVE32: [[C12:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 13
138 ; WAVE32: [[ICMP12:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C12]]
231 ; WAVE64: [[C12:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 13
232 ; WAVE64: [[ICMP12:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C12]]
283 ; WAVE32: [[C12:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 13
284 ; WAVE32: [[ICMP12:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C12]]
594 ; WAVE64: [[C12:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 12
595 ; WAVE64: [[ICMP11:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[ADD]](s32), [[C12]]
[all …]
Dlegalize-implicit-def-s1025.mir65 ; TAHITI: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
66 ; TAHITI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
130 ; TAHITI: [[COPY50:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
195 ; TAHITI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND41]], [[C12]](s32)
322 ; FIJI: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 12
323 ; FIJI: [[LSHR12:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C12]](s16)
341 ; FIJI: [[LSHR27:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C12]](s16)
Dlegalize-merge-values.mir374 ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
375 ; CHECK: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C12]](s32)
427 ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
428 ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[C12]](s32)
550 ; CHECK: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
551 ; CHECK: [[AND4:%[0-9]+]]:_(s16) = G_AND [[C12]], [[C7]]
775 ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
776 ; CHECK: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND12]], [[C12]](s32)
921 ; CHECK: [[SHL42:%[0-9]+]]:_(s32) = G_SHL [[AND44]], [[C12]](s32)
1038 ; CHECK: [[SHL73:%[0-9]+]]:_(s32) = G_SHL [[COPY76]], [[C12]](s32)
Dlegalize-insert-vector-elt.mir237 ; CHECK: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 208
238 ; CHECK: [[PTR_ADD12:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY1]], [[C12]](s64)
275 ; CHECK: [[PTR_ADD27:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY2]], [[C12]](s64)
349 ; CHECK: [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 176
350 ; CHECK: [[PTR_ADD13:%[0-9]+]]:_(p1) = G_PTR_ADD [[COPY1]], [[C12]](s64)
431 ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 36
432 ; CHECK: [[PTR_ADD11:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C12]](s32)
/external/cldr/tools/java/org/unicode/cldr/draft/keyboard/
DIsoLayoutPosition.java39 …"L"), C10('C', 10, ";"), C11('C', 11, "'"), C12('C', 12, "(key to right of ')"), // Additional key… enumConstant
/external/llvm-project/clang/test/Parser/
Dcxx2a-concept-declaration.cpp74 template<bool x> concept C12 = 2 && x; // expected-error {{atomic constraint must be of type 'bool'…
/external/python/cpython3/PCbuild/
Dpcbuild.sln75 …0-8D11-00A0C91BC942}") = "pywlauncher", "pywlauncher.vcxproj", "{1D4B18D3-7C12-4ECB-9179-8531FF876…
1032 {1D4B18D3-7C12-4ECB-9179-8531FF876CE6}.Debug|ARM.ActiveCfg = Debug|ARM
1033 {1D4B18D3-7C12-4ECB-9179-8531FF876CE6}.Debug|ARM.Build.0 = Debug|ARM
1034 {1D4B18D3-7C12-4ECB-9179-8531FF876CE6}.Debug|ARM64.ActiveCfg = Debug|ARM64
1035 {1D4B18D3-7C12-4ECB-9179-8531FF876CE6}.Debug|ARM64.Build.0 = Debug|ARM64
1036 {1D4B18D3-7C12-4ECB-9179-8531FF876CE6}.Debug|Win32.ActiveCfg = Debug|Win32
1037 {1D4B18D3-7C12-4ECB-9179-8531FF876CE6}.Debug|Win32.Build.0 = Debug|Win32
1038 {1D4B18D3-7C12-4ECB-9179-8531FF876CE6}.Debug|x64.ActiveCfg = Debug|x64
1039 {1D4B18D3-7C12-4ECB-9179-8531FF876CE6}.Debug|x64.Build.0 = Debug|x64
1040 {1D4B18D3-7C12-4ECB-9179-8531FF876CE6}.PGInstrument|ARM.ActiveCfg = PGInstrument|ARM
[all …]
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td225 def C12 : Ri< 12, "C12">;
308 def C12_C13 : Rdi<12, "C12", [C12, C13]>;
/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td226 def C12 : Ri< 12, "C12">;
309 def C12_C13 : Rdi<12, "C12", [C12, C13]>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td225 def C12 : Ri< 12, "C12">;
308 def C12_C13 : Rdi<12, "C12", [C12, C13]>;
/external/llvm-project/clang/test/SemaCXX/
Dfriend2.cpp100 template<typename T> class C12 { class
/external/harfbuzz_ng/test/shaping/data/in-house/tests/
Dindic-vowel-letter-spoofing.tests41 ../fonts/03e3f463c3a985bc42096620cc415342818454fb.ttf::U+0C13,U+0020,U+0C12,U+0C55:[gid3=0+1497|gid…
42 ../fonts/03e3f463c3a985bc42096620cc415342818454fb.ttf::U+0C14,U+0020,U+0C12,U+0C4C:[gid4=0+1497|gid…
Duse-vowel-letter-spoofing.tests48 ../fonts/46669c8860cbfea13562a6ca0d83130ee571137b.ttf::U+0C12,U+0C4C:[uni0C12=0+500|uni25CC=0+500|u…
49 ../fonts/46669c8860cbfea13562a6ca0d83130ee571137b.ttf::U+0C12,U+0C55:[uni0C12=0+500|uni25CC=0+500|u…
/external/harfbuzz_ng/src/
DHBIndicVowelConstraints.txt51 0C12 0C55 ; # TELUGU LETTER O, TELUGU LENGTH MARK
52 0C12 0C4C ; # TELUGU LETTER O, TELUGU VOWEL SIGN AU
/external/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCTargetDesc.cpp124 SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCTargetDesc.cpp124 SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15

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