| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 76 const DebugLoc &DL, unsigned DReg,
90 const DebugLoc &DL, unsigned DReg,
148 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR() local
150 if (DReg != ARM::NoRegister) return ARM::ssub_1; in getDPRLaneFromSPR()
446 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg() argument
453 .addReg(DReg, 0, Lane); in createExtractSubreg()
493 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg() argument
499 .addReg(DReg) in createInsertSubreg()
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| D | ARMBaseInstrInfo.cpp | 4219 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane() local
4222 if (DReg != ARM::NoRegister) in getCorrespondingDRegAndLane()
4223 return DReg; in getCorrespondingDRegAndLane()
4226 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4228 assert(DReg && "S-register with no D super-register?"); in getCorrespondingDRegAndLane()
4229 return DReg; in getCorrespondingDRegAndLane()
4248 MachineInstr &MI, unsigned DReg, in getImplicitSPRUseForDPRUse() argument
4252 if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) { in getImplicitSPRUseForDPRUse()
4258 ImplicitSReg = TRI->getSubReg(DReg, in getImplicitSPRUseForDPRUse()
4276 unsigned DstReg, SrcReg, DReg; in setExecutionDomain() local
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 73 const DebugLoc &DL, unsigned DReg,
87 const DebugLoc &DL, unsigned DReg,
145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR() local
147 if (DReg != ARM::NoRegister) return ARM::ssub_1; in getDPRLaneFromSPR()
434 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg() argument
441 .addReg(DReg, 0, Lane); in createExtractSubreg()
479 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg() argument
485 .addReg(DReg) in createInsertSubreg()
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| D | ARMBaseInstrInfo.cpp | 4904 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane() local
4907 if (DReg != ARM::NoRegister) in getCorrespondingDRegAndLane()
4908 return DReg; in getCorrespondingDRegAndLane()
4911 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4913 assert(DReg && "S-register with no D super-register?"); in getCorrespondingDRegAndLane()
4914 return DReg; in getCorrespondingDRegAndLane()
4933 MachineInstr &MI, unsigned DReg, in getImplicitSPRUseForDPRUse() argument
4937 if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) { in getImplicitSPRUseForDPRUse()
4943 ImplicitSReg = TRI->getSubReg(DReg, in getImplicitSPRUseForDPRUse()
4961 unsigned DstReg, SrcReg, DReg; in setExecutionDomain() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 73 const DebugLoc &DL, unsigned DReg,
87 const DebugLoc &DL, unsigned DReg,
145 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, in getDPRLaneFromSPR() local
147 if (DReg != ARM::NoRegister) return ARM::ssub_1; in getDPRLaneFromSPR()
434 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg() argument
441 .addReg(DReg, 0, Lane); in createExtractSubreg()
479 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg() argument
485 .addReg(DReg) in createInsertSubreg()
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| D | ARMBaseInstrInfo.cpp | 4868 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass); in getCorrespondingDRegAndLane() local
4871 if (DReg != ARM::NoRegister) in getCorrespondingDRegAndLane()
4872 return DReg; in getCorrespondingDRegAndLane()
4875 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass); in getCorrespondingDRegAndLane()
4877 assert(DReg && "S-register with no D super-register?"); in getCorrespondingDRegAndLane()
4878 return DReg; in getCorrespondingDRegAndLane()
4897 MachineInstr &MI, unsigned DReg, in getImplicitSPRUseForDPRUse() argument
4901 if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) { in getImplicitSPRUseForDPRUse()
4907 ImplicitSReg = TRI->getSubReg(DReg, in getImplicitSPRUseForDPRUse()
4925 unsigned DstReg, SrcReg, DReg; in setExecutionDomain() local
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | Mips16FrameLowering.cpp | 79 unsigned DReg = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
81 MCCFIInstruction::createOffset(nullptr, DReg, Offset)); in emitPrologue()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16FrameLowering.cpp | 73 unsigned DReg = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
75 MCCFIInstruction::createOffset(nullptr, DReg, Offset)); in emitPrologue()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | Mips16FrameLowering.cpp | 79 unsigned DReg = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
81 MCCFIInstruction::createOffset(nullptr, DReg, Offset)); in emitPrologue()
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| /external/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 860 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local
861 DEBUG(dbgs() << "Renaming %FP" << KReg << " as imp %FP" << DReg << "\n"); in adjustLiveRegs()
862 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]); in adjustLiveRegs()
863 std::swap(RegMap[KReg], RegMap[DReg]); in adjustLiveRegs()
865 Defs &= ~(1 << DReg); in adjustLiveRegs()
891 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local
892 DEBUG(dbgs() << "Defining %FP" << DReg << " as 0\n"); in adjustLiveRegs()
894 pushReg(DReg); in adjustLiveRegs()
895 Defs &= ~(1 << DReg); in adjustLiveRegs()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 907 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local
908 LLVM_DEBUG(dbgs() << "Renaming %fp" << KReg << " as imp %fp" << DReg in adjustLiveRegs()
910 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]); in adjustLiveRegs()
911 std::swap(RegMap[KReg], RegMap[DReg]); in adjustLiveRegs()
913 Defs &= ~(1 << DReg); in adjustLiveRegs()
939 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local
940 LLVM_DEBUG(dbgs() << "Defining %fp" << DReg << " as 0\n"); in adjustLiveRegs()
942 pushReg(DReg); in adjustLiveRegs()
943 Defs &= ~(1 << DReg); in adjustLiveRegs()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 907 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local
908 LLVM_DEBUG(dbgs() << "Renaming %fp" << KReg << " as imp %fp" << DReg in adjustLiveRegs()
910 std::swap(Stack[getSlot(KReg)], Stack[getSlot(DReg)]); in adjustLiveRegs()
911 std::swap(RegMap[KReg], RegMap[DReg]); in adjustLiveRegs()
913 Defs &= ~(1 << DReg); in adjustLiveRegs()
939 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs() local
940 LLVM_DEBUG(dbgs() << "Defining %fp" << DReg << " as 0\n"); in adjustLiveRegs()
942 pushReg(DReg); in adjustLiveRegs()
943 Defs &= ~(1 << DReg); in adjustLiveRegs()
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3386 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotation() local
3389 unsigned TmpReg = DReg; in expandRotation()
3396 if (DReg == SReg) { in expandRotation()
3404 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandRotation()
3409 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
3437 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
3438 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandRotation()
3451 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotationImm() local
3465 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); in expandRotationImm()
3470 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); in expandRotationImm()
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| /external/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4860 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotation() local
4863 unsigned TmpReg = DReg; in expandRotation()
4869 if (DReg == SReg) { in expandRotation()
4877 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandRotation()
4882 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4909 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4910 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandRotation()
4923 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotationImm() local
4936 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); in expandRotationImm()
4941 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); in expandRotationImm()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4750 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotation() local
4753 unsigned TmpReg = DReg; in expandRotation()
4759 if (DReg == SReg) { in expandRotation()
4767 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI); in expandRotation()
4772 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4799 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI); in expandRotation()
4800 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI); in expandRotation()
4813 unsigned DReg = Inst.getOperand(0).getReg(); in expandRotationImm() local
4826 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI); in expandRotationImm()
4831 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI); in expandRotationImm()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 347 Register DReg = DstInst->getOperand(0).getReg(); in adjustSchedDependency() local
352 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) { in adjustSchedDependency()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 418 Register DReg = DstInst->getOperand(0).getReg(); in adjustSchedDependency() local
423 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) { in adjustSchedDependency()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 199 IValueT DReg = EncodedQReg << 1; in mapQRegToDReg() local
200 assert(DReg < RegARM32::getNumDRegs()); in mapQRegToDReg()
201 return DReg; in mapQRegToDReg()
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 3377 unsigned DReg = RISCV::F0_D + RegNo; in getRegForInlineAsmConstraint() local
3378 return std::make_pair(DReg, &RISCV::FPR64RegClass); in getRegForInlineAsmConstraint()
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