Searched refs:EL2 (Results 1 – 25 of 31) sorted by relevance
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10 participant "SDEI client" as EL214 activate EL215 EL2->EL3: **SDEI_INTERRUPT_BIND**(irq)16 EL3->EL2: event number: ev17 EL2->EL3: **SDEI_EVENT_REGISTER**(ev, handler, ...)18 EL3->EL2: success19 EL2->EL3: **SDEI_EVENT_ENABLE**(ev)20 EL3->EL2: success21 EL2->EL3: **SDEI_PE_UNMASK**()22 EL3->EL2: 1[all …]
10 participant "SDEI client" as EL215 activate EL216 EL2->EL3: **SDEI_EVENT_REGISTER**(ev, handler, ...)17 EL3->EL2: success18 EL2->EL3: **SDEI_EVENT_ENABLE**(ev)19 EL3->EL2: success20 EL2->EL3: **SDEI_PE_UNMASK**()21 EL3->EL2: 136 SDEI->EL2: dispatch37 activate EL2 #salmon[all …]
91 - If set to ``1``, will increment the associated ``PMEVCNTR<n>`` at EL2.92 - Reserved if EL2 not implemented.98 at Secure EL2.99 - Reserved if Secure EL2 not implemented.135 counting (by ``PMEVCNTR<n>``) is prohibited (e.g. EL2 and the Secure
8 This port is a minimal port to support loading non-secure EL2 payloads such30 "kernel", as BL31 will drop into AArch64/EL2 to the respective load address.48 see some text from BL31, followed by the output of the EL2 payload.81 the EL2 payload needs to be a Linux kernel, a bootloader or any other kernel
35 SD card, it will load it and execute in EL2 in AArch64. Basically, it executes54 in AArch32. This means that BL33 can't be in EL2 in AArch64 mode. The56 is used for EL2. When using a AArch64 kernel, it should simply start in EL2.152 level. If BL33 was running in EL2 in AArch64 (as in the default bootflow of205 By default this option is 0, which means that TF-A will jump to BL33 in EL2
64 multiple normal world SMC clients lies with EL2 software. When present, EL271 and are therefore unaffected by this issue. Other EL2 software should be audited74 EL2 software might find mitigating this threat somewhat onerous, because for all
21 …0 0x00 0x00 0x00 0x00 0x00 0x00 ]; I_CTXT : Context Packet.; Ctxt: AArch64,EL2, NS; CID=0x00000000…29 …0 0x00 0x00 0x00 0x00 0x00 0x00 ]; I_CTXT : Context Packet.; Ctxt: AArch64,EL2, NS; CID=0x00000000…
69 resides at EL3 and S-EL2 (or EL3 and S-EL1).73 used as a reference code base for an S-EL2 secure firmware on79 - Hypervisor refers to the NS-EL2 component managing Virtual Machines (or81 - SPMC refers to the S-EL2 component managing Virtual Machines (or Secure94 kernel) to SPMC located either at S-EL1 or S-EL2.100 - S-EL2 supporting platforms implementing Armv8.4-SecEL2 extension.101 SPMD conveys FF-A protocol from EL3 to S-EL2.123 level to being S-EL1 or S-EL2. It defaults to enabled (value 1) when126 restoring) the EL2 system register context before entering (resp.141 | SPMC at S-EL2 (e.g. Hafnium) | 1 | 1 (default when |[all …]
26 at EL2 and an event dispatch resulting from the triggering of a bound interrupt.41 original EL2 execution [13]. Note that the SDEI interrupt remains active until200 - EL2, if EL2 is implemented. The Hypervisor is expected to implement a204 - Non-secure EL1, if EL2 is not implemented or disabled.
36 Exception Level (either EL2, or NS EL1 if EL2 isn't implemented) to request to
114 - a test payload, bootloader or hypervisor running at NS-EL2
67 ; CHECK: [[EL2:%[a-zA-Z0-9_]+]] = extractelement <4 x float> [[VEC4]], i32 168 ; CHECK: store float [[EL2]]
92 enum ExceptionLevel { EL0 = 0, EL1 = 1, EL2 = 2, EL3 = 3 }; enumerator
500 when EL2 in BranchTo()
68 at Secure EL1, Secure EL2 (if implemented) and EL3.
448 space=EL2
170 // CHECK: %[[EL2:.*]] = tensor.extract %[[SHAPE]]{{\[}}%[[C2]]] : tensor<3xi64>171 // CHECK: %[[SIZE_2:.*]] = index_cast %[[EL2]] : i64 to index
26 register accesses from EL1/EL2 to EL397 virtualization in EL2 context switches if the architecture supports it200 top of Hafnium in S-EL2443 routine in EL2571 - Build option to support EL2 context save and restore in the secure world576 be done as part of future S-EL2/SPM development.595 or S-EL2 (SPMD_SPM_AT_SEL2).650 - el3_runtime: Add support for enabling S-EL2943 - socionext: uniphier: Run BL33 at EL2, call uniphier_scp_is_running() only1639 - Enabled MPAM EL2 traps (``MPAMHCR_EL2`` and ``MPAM_EL2``)[all …]
161 operations when entering/exiting an EL2 execution context. This is of primary171 Armv8.4-NV registers to be saved/restored when entering/exiting an EL2593 component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2743 If this option is enabled for the EL3 software then EL2 software also must
212 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0)252 - ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the253 ``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by609 EL3 Runtime Software initializes the EL2 or EL1 processor context for normal-613 at the highest available Exception Level (EL2 if available, otherwise EL1).862 context between the normal world (EL1/EL2) and trusted world (Secure-EL1).1093 communication with the normal-world software running in EL1/EL2. Communication1152 will exit to EL2 and run BL33.1175 reports the general purpose, EL3, Secure EL1 and some EL2 state registers.
40 Secure-EL1, Non-secure EL1 or EL2 depending upon the security state of the42 or EL2.578 non-secure state (EL1/EL2) and are not visible to the SP. This routing
199 - __Update__: Memaccess: Add EL2 secure memory space flag.
510 $(error SPMD with SPM at S-EL2 requires CTX_INCLUDE_EL2_REGS option)