| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86InsertWait.cpp | 87 case X86::FINCSTP: in isX87ControlInstruction()
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| D | X86ScheduleZnver2.td | 923 // FINCSTP FDECSTP.
924 def : InstRW<[Zn2WriteFPU3], (instrs FINCSTP, FDECSTP)>;
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| D | X86ScheduleZnver1.td | 914 // FINCSTP FDECSTP.
915 def : InstRW<[ZnWriteFPU3], (instrs FINCSTP, FDECSTP)>;
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| D | X86ScheduleAtom.td | 552 def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT,
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| D | X86SchedSandyBridge.td | 599 def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP,
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| D | X86InstrFPStack.td | 732 def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>;
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| D | X86SchedBroadwell.td | 647 def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>;
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| D | X86SchedHaswell.td | 910 def: InstRW<[HWWriteResGroup6], (instrs FINCSTP, FNOP)>;
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| D | X86SchedSkylakeClient.td | 647 def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;
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| D | X86SchedSkylakeServer.td | 662 def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ScheduleZnver2.td | 911 // FINCSTP FDECSTP.
912 def : InstRW<[Zn2WriteFPU3], (instrs FINCSTP, FDECSTP)>;
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| D | X86ScheduleZnver1.td | 911 // FINCSTP FDECSTP.
912 def : InstRW<[ZnWriteFPU3], (instrs FINCSTP, FDECSTP)>;
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| D | X86ScheduleAtom.td | 549 def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT,
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| D | X86SchedSandyBridge.td | 596 def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP,
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| D | X86InstrFPStack.td | 736 def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>;
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| D | X86SchedBroadwell.td | 644 def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>;
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| D | X86SchedSkylakeClient.td | 644 def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;
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| D | X86SchedHaswell.td | 907 def: InstRW<[HWWriteResGroup6], (instrs FINCSTP, FNOP)>;
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| D | X86SchedSkylakeServer.td | 657 def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;
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| /external/llvm/lib/Target/X86/ |
| D | X86SchedHaswell.td | 1169 // FINCSTP FDECSTP.
1170 def : InstRW<[WriteP01], (instregex "FINCSTP", "FDECSTP")>;
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| D | X86InstrFPStack.td | 658 def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", [], IIC_FPSTP>;
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| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 729 #define FINCSTP CHOICE(fincstp, fincstp, fincstp) macro
1442 #define FINCSTP fincstp macro
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenSubtargetInfo.inc | 6505 {DBGFIELD("FINCSTP") 1, false, false, 1, 1, 1, 1, 0, 0}, // #816
7882 {DBGFIELD("FINCSTP") 1, false, false, 96, 2, 2, 1, 0, 0}, // #816
9259 {DBGFIELD("FINCSTP") 1, false, false, 1173, 4, 1, 1, 0, 0}, // #816
10636 {DBGFIELD("FINCSTP") 1, false, false, 1, 1, 2, 1, 0, 0}, // #816
12013 {DBGFIELD("FINCSTP") 1, false, false, 2689, 5, 1, 1, 0, 0}, // #816
13390 {DBGFIELD("FINCSTP") 1, false, false, 3706, 5, 1, 1, 0, 0}, // #816
14767 {DBGFIELD("FINCSTP") 1, false, false, 1173, 4, 1, 1, 0, 0}, // #816
16144 {DBGFIELD("FINCSTP") 1, false, false, 3805, 2, 2, 1, 0, 0}, // #816
17521 {DBGFIELD("FINCSTP") 1, false, false, 2689, 5, 1, 1, 0, 0}, // #816
18898 {DBGFIELD("FINCSTP") 1, false, false, 4719, 7, 9, 1, 0, 0}, // #816
[all …]
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| /external/capstone/arch/X86/ |
| D | X86GenAsmWriter1.inc | 792 10717U, // FINCSTP
9649 0U, // FINCSTP
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| D | X86GenAsmWriter.inc | 792 13357U, // FINCSTP
9649 0U, // FINCSTP
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