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Searched refs:Falkor (Results 1 – 20 of 20) sorted by relevance

/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SchedFalkor.td1 //==- AArch64SchedFalkor.td - Falkor Scheduling Definitions -*- tablegen -*-==//
9 // This file defines the machine model for Qualcomm Falkor to support
33 // Define each kind of processor resource and number available on Falkor.
64 // Falkor.
68 // These WriteRes entries are not used in the Falkor sched model.
103 // These ReadAdvance entries are not used in the Falkor sched model.
DAArch64Subtarget.cpp131 case Falkor: in initializeProperties()
DAArch64FalkorHWPFFix.cpp124 if (ST->getProcFamily() != AArch64Subtarget::Falkor) in runOnFunction()
817 if (ST.getProcFamily() != AArch64Subtarget::Falkor) in runOnMachineFunction()
DAArch64Subtarget.h63 Falkor, enumerator
DAArch64SchedFalkorDetails.td1 //==- AArch64SchedFalkorDetails.td - Falkor Scheduling Defs -*- tablegen -*-==//
10 // Qualcomm Falkor subtarget.
14 // Contains all of the Falkor specific SchedWriteRes types. The approach
26 // Contains all of the Falkor specific ReadAdvance types for forwarding logic.
28 // Contains all of the Falkor specific WriteVariant types for immediate zero
DAArch64.td863 def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
864 "Qualcomm Falkor processors", [
DAArch64TargetTransformInfo.cpp936 if (ST->getProcFamily() == AArch64Subtarget::Falkor && in getUnrollingPreferences()
DAArch64ISelLowering.cpp10867 if (Subtarget->getProcFamily() == AArch64Subtarget::Falkor && in getTargetMMOFlags()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SchedFalkor.td1 //==- AArch64SchedFalkor.td - Falkor Scheduling Definitions -*- tablegen -*-==//
9 // This file defines the machine model for Qualcomm Falkor to support
33 // Define each kind of processor resource and number available on Falkor.
64 // Falkor.
68 // These WriteRes entries are not used in the Falkor sched model.
103 // These ReadAdvance entries are not used in the Falkor sched model.
DAArch64Subtarget.cpp107 case Falkor: in initializeProperties()
DAArch64Subtarget.h56 Falkor, enumerator
DAArch64FalkorHWPFFix.cpp124 if (ST->getProcFamily() != AArch64Subtarget::Falkor) in runOnFunction()
817 if (ST.getProcFamily() != AArch64Subtarget::Falkor) in runOnMachineFunction()
DAArch64SchedFalkorDetails.td1 //==- AArch64SchedFalkorDetails.td - Falkor Scheduling Defs -*- tablegen -*-==//
10 // Qualcomm Falkor subtarget.
14 // Contains all of the Falkor specific SchedWriteRes types. The approach
26 // Contains all of the Falkor specific ReadAdvance types for forwarding logic.
28 // Contains all of the Falkor specific WriteVariant types for immediate zero
DAArch64.td712 def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
713 "Qualcomm Falkor processors", [
DAArch64TargetTransformInfo.cpp790 if (ST->getProcFamily() == AArch64Subtarget::Falkor && in getUnrollingPreferences()
DAArch64ISelLowering.cpp9094 if (Subtarget->getProcFamily() == AArch64Subtarget::Falkor && in getMMOFlags()
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dfalkor-hwpf-fix.ll3 ; Check that strided load tag collisions are avoided on Falkor.
Dfalkor-hwpf.ll4 ; Check that strided access metadata is added to loads in inner loops when compiling for Falkor.
DO3-pipeline.ll33 ; CHECK-NEXT: Falkor HW Prefetch Fix
186 ; CHECK-NEXT: Falkor HW Prefetch Fix Late Phase
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenSubtargetInfo.inc232 …{ "falkor", "Qualcomm Falkor processors", AArch64::ProcFalkor, { { { 0x581200101800800ULL, 0x10002…
19333 if (Bits[AArch64::ProcFalkor] && ARMProcFamily < Falkor) ARMProcFamily = Falkor;