1//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing. 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// AArch64 Subtarget features. 20// 21 22def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true", 23 "Enable ARMv8 FP">; 24 25def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", 26 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>; 27 28def FeatureSM4 : SubtargetFeature< 29 "sm4", "HasSM4", "true", 30 "Enable SM3 and SM4 support", [FeatureNEON]>; 31 32def FeatureSHA2 : SubtargetFeature< 33 "sha2", "HasSHA2", "true", 34 "Enable SHA1 and SHA256 support", [FeatureNEON]>; 35 36def FeatureSHA3 : SubtargetFeature< 37 "sha3", "HasSHA3", "true", 38 "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>; 39 40def FeatureAES : SubtargetFeature< 41 "aes", "HasAES", "true", 42 "Enable AES support", [FeatureNEON]>; 43 44// Crypto has been split up and any combination is now valid (see the 45// crypto definitions above). Also, crypto is now context sensitive: 46// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2. 47// Therefore, we rely on Clang, the user interacing tool, to pass on the 48// appropriate crypto options. But here in the backend, crypto has very little 49// meaning anymore. We kept the Crypto definition here for backward 50// compatibility, and now imply features SHA2 and AES, which was the 51// "traditional" meaning of Crypto. 52def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", 53 "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>; 54 55def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", 56 "Enable ARMv8 CRC-32 checksum instructions">; 57 58def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", 59 "Enable ARMv8 Reliability, Availability and Serviceability Extensions">; 60 61def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true", 62 "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">; 63 64def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true", 65 "Enable out of line atomics to support LSE instructions">; 66 67def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true", 68 "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">; 69 70def FeaturePAN : SubtargetFeature< 71 "pan", "HasPAN", "true", 72 "Enables ARM v8.1 Privileged Access-Never extension">; 73 74def FeatureLOR : SubtargetFeature< 75 "lor", "HasLOR", "true", 76 "Enables ARM v8.1 Limited Ordering Regions extension">; 77 78def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2", 79 "true", "Enable RW operand CONTEXTIDR_EL2" >; 80 81def FeatureVH : SubtargetFeature<"vh", "HasVH", "true", 82 "Enables ARM v8.1 Virtual Host extension", [FeatureCONTEXTIDREL2] >; 83 84def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", 85 "Enable ARMv8 PMUv3 Performance Monitors extension">; 86 87def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", 88 "Full FP16", [FeatureFPARMv8]>; 89 90def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", 91 "Enable FP16 FML instructions", [FeatureFullFP16]>; 92 93def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true", 94 "Enable Statistical Profiling extension">; 95 96def FeaturePAN_RWV : SubtargetFeature< 97 "pan-rwv", "HasPAN_RWV", "true", 98 "Enable v8.2 PAN s1e1R and s1e1W Variants", 99 [FeaturePAN]>; 100 101// UAO PState 102def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true", 103 "Enable v8.2 UAO PState">; 104 105def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP", 106 "true", "Enable v8.2 data Cache Clean to Point of Persistence" >; 107 108def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true", 109 "Enable Scalable Vector Extension (SVE) instructions", [FeatureFullFP16]>; 110 111// This flag is currently still labeled as Experimental, but when fully 112// implemented this should tell the compiler to use the zeroing pseudos to 113// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive 114// lanes are known to be zero. The pseudos will then be expanded using the 115// MOVPRFX instruction to zero the inactive lanes. This feature should only be 116// enabled if MOVPRFX instructions are known to merge with the destructive 117// operations they prefix. 118// 119// This feature could similarly be extended to support cheap merging of _any_ 120// value into the inactive lanes using the MOVPRFX instruction that uses 121// merging-predication. 122def FeatureExperimentalZeroingPseudos 123 : SubtargetFeature<"use-experimental-zeroing-pseudos", 124 "UseExperimentalZeroingPseudos", "true", 125 "Hint to the compiler that the MOVPRFX instruction is " 126 "merged with destructive operations", 127 []>; 128 129def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true", 130 "Enable Scalable Vector Extension 2 (SVE2) instructions", [FeatureSVE]>; 131 132def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true", 133 "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>; 134 135def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true", 136 "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>; 137 138def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true", 139 "Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>; 140 141def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true", 142 "Enable bit permutation SVE2 instructions", [FeatureSVE2]>; 143 144def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", 145 "Has zero-cycle register moves">; 146 147def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true", 148 "Has zero-cycle zeroing instructions for generic registers">; 149 150def FeatureZCZeroingFP : SubtargetFeature<"zcz-fp", "HasZeroCycleZeroingFP", "true", 151 "Has zero-cycle zeroing instructions for FP registers">; 152 153def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", 154 "Has zero-cycle zeroing instructions", 155 [FeatureZCZeroingGP, FeatureZCZeroingFP]>; 156 157/// ... but the floating-point version doesn't quite work in rare cases on older 158/// CPUs. 159def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround", 160 "HasZeroCycleZeroingFPWorkaround", "true", 161 "The zero-cycle floating-point zeroing instruction has a bug">; 162 163def FeatureStrictAlign : SubtargetFeature<"strict-align", 164 "StrictAlign", "true", 165 "Disallow all unaligned memory " 166 "access">; 167 168foreach i = {1-7,9-15,18,20-28,30} in 169 def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true", 170 "Reserve X"#i#", making it unavailable " 171 "as a GPR">; 172 173foreach i = {8-15,18} in 174 def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i, 175 "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">; 176 177def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", 178 "Use alias analysis during codegen">; 179 180def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps", 181 "true", 182 "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">; 183 184def FeaturePredictableSelectIsExpensive : SubtargetFeature< 185 "predictable-select-expensive", "PredictableSelectIsExpensive", "true", 186 "Prefer likely predicted branches over selects">; 187 188def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move", 189 "CustomAsCheapAsMove", "true", 190 "Use custom handling of cheap instructions">; 191 192def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move", 193 "ExynosAsCheapAsMove", "true", 194 "Use Exynos specific handling of cheap instructions", 195 [FeatureCustomCheapAsMoveHandling]>; 196 197def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", 198 "UsePostRAScheduler", "true", "Schedule again after register allocation">; 199 200def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store", 201 "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">; 202 203def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128", 204 "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">; 205 206def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow", 207 "true", "STR of Q register with register offset is slow">; 208 209def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature< 210 "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern", 211 "true", "Use alternative pattern for sextload convert to f32">; 212 213def FeatureArithmeticBccFusion : SubtargetFeature< 214 "arith-bcc-fusion", "HasArithmeticBccFusion", "true", 215 "CPU fuses arithmetic+bcc operations">; 216 217def FeatureArithmeticCbzFusion : SubtargetFeature< 218 "arith-cbz-fusion", "HasArithmeticCbzFusion", "true", 219 "CPU fuses arithmetic + cbz/cbnz operations">; 220 221def FeatureFuseAddress : SubtargetFeature< 222 "fuse-address", "HasFuseAddress", "true", 223 "CPU fuses address generation and memory operations">; 224 225def FeatureFuseAES : SubtargetFeature< 226 "fuse-aes", "HasFuseAES", "true", 227 "CPU fuses AES crypto operations">; 228 229def FeatureFuseArithmeticLogic : SubtargetFeature< 230 "fuse-arith-logic", "HasFuseArithmeticLogic", "true", 231 "CPU fuses arithmetic and logic operations">; 232 233def FeatureFuseCCSelect : SubtargetFeature< 234 "fuse-csel", "HasFuseCCSelect", "true", 235 "CPU fuses conditional select operations">; 236 237def FeatureFuseCryptoEOR : SubtargetFeature< 238 "fuse-crypto-eor", "HasFuseCryptoEOR", "true", 239 "CPU fuses AES/PMULL and EOR operations">; 240 241def FeatureFuseLiterals : SubtargetFeature< 242 "fuse-literals", "HasFuseLiterals", "true", 243 "CPU fuses literal generation operations">; 244 245def FeatureDisableLatencySchedHeuristic : SubtargetFeature< 246 "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true", 247 "Disable latency scheduling heuristic">; 248 249def FeatureForce32BitJumpTables 250 : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true", 251 "Force jump table entries to be 32-bits wide except at MinSize">; 252 253def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true", 254 "Enable support for RCPC extension">; 255 256def FeatureUseRSqrt : SubtargetFeature< 257 "use-reciprocal-square-root", "UseRSqrt", "true", 258 "Use the reciprocal square root approximation">; 259 260def FeatureDotProd : SubtargetFeature< 261 "dotprod", "HasDotProd", "true", 262 "Enable dot product support">; 263 264def FeaturePA : SubtargetFeature< 265 "pa", "HasPA", "true", 266 "Enable v8.3-A Pointer Authentication extension">; 267 268def FeatureJS : SubtargetFeature< 269 "jsconv", "HasJS", "true", 270 "Enable v8.3-A JavaScript FP conversion instructions", 271 [FeatureFPARMv8]>; 272 273def FeatureCCIDX : SubtargetFeature< 274 "ccidx", "HasCCIDX", "true", 275 "Enable v8.3-A Extend of the CCSIDR number of sets">; 276 277def FeatureComplxNum : SubtargetFeature< 278 "complxnum", "HasComplxNum", "true", 279 "Enable v8.3-A Floating-point complex number support", 280 [FeatureNEON]>; 281 282def FeatureNV : SubtargetFeature< 283 "nv", "HasNV", "true", 284 "Enable v8.4-A Nested Virtualization Enchancement">; 285 286def FeatureMPAM : SubtargetFeature< 287 "mpam", "HasMPAM", "true", 288 "Enable v8.4-A Memory system Partitioning and Monitoring extension">; 289 290def FeatureDIT : SubtargetFeature< 291 "dit", "HasDIT", "true", 292 "Enable v8.4-A Data Independent Timing instructions">; 293 294def FeatureTRACEV8_4 : SubtargetFeature< 295 "tracev8.4", "HasTRACEV8_4", "true", 296 "Enable v8.4-A Trace extension">; 297 298def FeatureAM : SubtargetFeature< 299 "am", "HasAM", "true", 300 "Enable v8.4-A Activity Monitors extension">; 301 302def FeatureAMVS : SubtargetFeature< 303 "amvs", "HasAMVS", "true", 304 "Enable v8.6-A Activity Monitors Virtualization support", 305 [FeatureAM]>; 306 307def FeatureSEL2 : SubtargetFeature< 308 "sel2", "HasSEL2", "true", 309 "Enable v8.4-A Secure Exception Level 2 extension">; 310 311def FeaturePMU : SubtargetFeature< 312 "pmu", "HasPMU", "true", 313 "Enable v8.4-A PMU extension">; 314 315def FeatureTLB_RMI : SubtargetFeature< 316 "tlb-rmi", "HasTLB_RMI", "true", 317 "Enable v8.4-A TLB Range and Maintenance Instructions">; 318 319def FeatureFMI : SubtargetFeature< 320 "fmi", "HasFMI", "true", 321 "Enable v8.4-A Flag Manipulation Instructions">; 322 323// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset 324def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true", 325 "Enable v8.4-A RCPC instructions with Immediate Offsets", 326 [FeatureRCPC]>; 327 328def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", 329 "NegativeImmediates", "false", 330 "Convert immediates and instructions " 331 "to their negated or complemented " 332 "equivalent when the immediate does " 333 "not fit in the encoding.">; 334 335def FeatureLSLFast : SubtargetFeature< 336 "lsl-fast", "HasLSLFast", "true", 337 "CPU has a fastpath logical shift of up to 3 places">; 338 339def FeatureAggressiveFMA : 340 SubtargetFeature<"aggressive-fma", 341 "HasAggressiveFMA", 342 "true", 343 "Enable Aggressive FMA for floating-point.">; 344 345def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true", 346 "Enable alternative NZCV format for floating point comparisons">; 347 348def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true", 349 "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to " 350 "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >; 351 352def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict", 353 "true", "Enable architectural speculation restriction" >; 354 355def FeatureSB : SubtargetFeature<"sb", "HasSB", 356 "true", "Enable v8.5 Speculation Barrier" >; 357 358def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS", 359 "true", "Enable Speculative Store Bypass Safe bit" >; 360 361def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true", 362 "Enable v8.5a execution and data prediction invalidation instructions" >; 363 364def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP", 365 "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >; 366 367def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI", 368 "true", "Enable Branch Target Identification" >; 369 370def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen", 371 "true", "Enable Random Number generation instructions" >; 372 373def FeatureMTE : SubtargetFeature<"mte", "HasMTE", 374 "true", "Enable Memory Tagging Extension" >; 375 376def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE", 377 "true", "Enable Trace Buffer Extension">; 378 379def FeatureETE : SubtargetFeature<"ete", "HasETE", 380 "true", "Enable Embedded Trace Extension", 381 [FeatureTRBE]>; 382 383def FeatureTME : SubtargetFeature<"tme", "HasTME", 384 "true", "Enable Transactional Memory Extension" >; 385 386def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals", 387 "AllowTaggedGlobals", 388 "true", "Use an instruction sequence for taking the address of a global " 389 "that allows a memory tag in the upper address bits">; 390 391def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16", 392 "true", "Enable BFloat16 Extension" >; 393 394def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8", 395 "true", "Enable Matrix Multiply Int8 Extension">; 396 397def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32", 398 "true", "Enable Matrix Multiply FP32 Extension", [FeatureSVE]>; 399 400def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64", 401 "true", "Enable Matrix Multiply FP64 Extension", [FeatureSVE]>; 402 403def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps", 404 "true", "Enable fine grained virtualization traps extension">; 405 406def FeatureEnhancedCounterVirtualization : 407 SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization", 408 "true", "Enable enhanced counter virtualization extension">; 409 410//===----------------------------------------------------------------------===// 411// Architectures. 412// 413 414def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", 415 "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM, 416 FeaturePAN, FeatureLOR, FeatureVH]>; 417 418def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", 419 "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO, 420 FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>; 421 422def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", 423 "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePA, 424 FeatureJS, FeatureCCIDX, FeatureComplxNum]>; 425 426def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", 427 "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd, 428 FeatureNV, FeatureMPAM, FeatureDIT, 429 FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeaturePMU, FeatureTLB_RMI, 430 FeatureFMI, FeatureRCPC_IMMO]>; 431 432def HasV8_5aOps : SubtargetFeature< 433 "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", 434 [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, 435 FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, 436 FeatureBranchTargetId]>; 437 438def HasV8_6aOps : SubtargetFeature< 439 "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions", 440 441 [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps, 442 FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>; 443 444def HasV8_0rOps : SubtargetFeature< 445 "v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions", 446 [//v8.1 447 FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2, 448 //v8.2 449 FeaturePerfMon, FeatureRAS, FeaturePsUAO, FeatureSM4, 450 FeatureSHA3, FeatureCCPP, FeatureFullFP16, FeaturePAN_RWV, 451 //v8.3 452 FeatureComplxNum, FeatureCCIDX, FeatureJS, 453 FeaturePA, FeatureRCPC, 454 //v8.4 455 FeatureDotProd, FeatureFP16FML, FeatureTRACEV8_4, 456 FeatureTLB_RMI, FeatureFMI, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO, 457 //v8.5 458 FeatureSSBS, FeaturePredRes, FeatureSB, FeatureSpecRestrict]>; 459 460//===----------------------------------------------------------------------===// 461// Register File Description 462//===----------------------------------------------------------------------===// 463 464include "AArch64RegisterInfo.td" 465include "AArch64RegisterBanks.td" 466include "AArch64CallingConvention.td" 467 468//===----------------------------------------------------------------------===// 469// Instruction Descriptions 470//===----------------------------------------------------------------------===// 471 472include "AArch64Schedule.td" 473include "AArch64InstrInfo.td" 474include "AArch64SchedPredicates.td" 475include "AArch64SchedPredExynos.td" 476include "AArch64Combine.td" 477 478def AArch64InstrInfo : InstrInfo; 479 480//===----------------------------------------------------------------------===// 481// Named operands for MRS/MSR/TLBI/... 482//===----------------------------------------------------------------------===// 483 484include "AArch64SystemOperands.td" 485 486//===----------------------------------------------------------------------===// 487// Access to privileged registers 488//===----------------------------------------------------------------------===// 489 490foreach i = 1-3 in 491def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP", 492 "true", "Permit use of TPIDR_EL"#i#" for the TLS base">; 493 494//===----------------------------------------------------------------------===// 495// Control codegen mitigation against Straight Line Speculation vulnerability. 496//===----------------------------------------------------------------------===// 497 498def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr", 499 "HardenSlsRetBr", "true", 500 "Harden against straight line speculation across RET and BR instructions">; 501def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr", 502 "HardenSlsBlr", "true", 503 "Harden against straight line speculation across BLR instructions">; 504 505//===----------------------------------------------------------------------===// 506// AArch64 Processors supported. 507// 508 509//===----------------------------------------------------------------------===// 510// Unsupported features to disable for scheduling models 511//===----------------------------------------------------------------------===// 512 513class AArch64Unsupported { list<Predicate> F; } 514 515def SVEUnsupported : AArch64Unsupported { 516 let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, 517 HasSVE2BitPerm]; 518} 519 520def PAUnsupported : AArch64Unsupported { 521 let F = [HasPA]; 522} 523 524include "AArch64SchedA53.td" 525include "AArch64SchedA55.td" 526include "AArch64SchedA57.td" 527include "AArch64SchedCyclone.td" 528include "AArch64SchedFalkor.td" 529include "AArch64SchedKryo.td" 530include "AArch64SchedExynosM3.td" 531include "AArch64SchedExynosM4.td" 532include "AArch64SchedExynosM5.td" 533include "AArch64SchedThunderX.td" 534include "AArch64SchedThunderX2T99.td" 535include "AArch64SchedThunderX3T110.td" 536include "AArch64SchedTSV110.td" 537 538def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", 539 "Cortex-A35 ARM processors", [ 540 FeatureCRC, 541 FeatureCrypto, 542 FeatureFPARMv8, 543 FeatureNEON, 544 FeaturePerfMon 545 ]>; 546 547def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", 548 "Cortex-A53 ARM processors", [ 549 FeatureBalanceFPOps, 550 FeatureCRC, 551 FeatureCrypto, 552 FeatureCustomCheapAsMoveHandling, 553 FeatureFPARMv8, 554 FeatureFuseAES, 555 FeatureNEON, 556 FeaturePerfMon, 557 FeaturePostRAScheduler, 558 FeatureUseAA 559 ]>; 560 561def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", 562 "Cortex-A55 ARM processors", [ 563 HasV8_2aOps, 564 FeatureCrypto, 565 FeatureFPARMv8, 566 FeatureFuseAES, 567 FeatureNEON, 568 FeatureFullFP16, 569 FeatureDotProd, 570 FeatureRCPC, 571 FeaturePerfMon 572 ]>; 573 574def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", 575 "Cortex-A57 ARM processors", [ 576 FeatureBalanceFPOps, 577 FeatureCRC, 578 FeatureCrypto, 579 FeatureCustomCheapAsMoveHandling, 580 FeatureFPARMv8, 581 FeatureFuseAES, 582 FeatureFuseLiterals, 583 FeatureNEON, 584 FeaturePerfMon, 585 FeaturePostRAScheduler, 586 FeaturePredictableSelectIsExpensive 587 ]>; 588 589def ProcA65 : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65", 590 "Cortex-A65 ARM processors", [ 591 HasV8_2aOps, 592 FeatureCrypto, 593 FeatureDotProd, 594 FeatureFPARMv8, 595 FeatureFullFP16, 596 FeatureNEON, 597 FeatureRAS, 598 FeatureRCPC, 599 FeatureSSBS, 600 ]>; 601 602def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", 603 "Cortex-A72 ARM processors", [ 604 FeatureCRC, 605 FeatureCrypto, 606 FeatureFPARMv8, 607 FeatureFuseAES, 608 FeatureNEON, 609 FeaturePerfMon 610 ]>; 611 612def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", 613 "Cortex-A73 ARM processors", [ 614 FeatureCRC, 615 FeatureCrypto, 616 FeatureFPARMv8, 617 FeatureFuseAES, 618 FeatureNEON, 619 FeaturePerfMon 620 ]>; 621 622def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", 623 "Cortex-A75 ARM processors", [ 624 HasV8_2aOps, 625 FeatureCrypto, 626 FeatureFPARMv8, 627 FeatureFuseAES, 628 FeatureNEON, 629 FeatureFullFP16, 630 FeatureDotProd, 631 FeatureRCPC, 632 FeaturePerfMon 633 ]>; 634 635def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", 636 "Cortex-A76 ARM processors", [ 637 HasV8_2aOps, 638 FeatureFPARMv8, 639 FeatureNEON, 640 FeatureRCPC, 641 FeatureCrypto, 642 FeatureFullFP16, 643 FeatureDotProd, 644 FeatureSSBS 645 ]>; 646 647def ProcA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77", 648 "Cortex-A77 ARM processors", [ 649 HasV8_2aOps, 650 FeatureFPARMv8, 651 FeatureNEON, FeatureRCPC, 652 FeatureCrypto, 653 FeatureFullFP16, 654 FeatureDotProd 655 ]>; 656 657def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily", 658 "CortexA78", 659 "Cortex-A78 ARM processors", [ 660 HasV8_2aOps, 661 FeatureCrypto, 662 FeatureFPARMv8, 663 FeatureFuseAES, 664 FeatureNEON, 665 FeatureRCPC, 666 FeaturePerfMon, 667 FeaturePostRAScheduler, 668 FeatureSPE, 669 FeatureFullFP16, 670 FeatureSSBS, 671 FeatureDotProd]>; 672 673def ProcR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily", 674 "CortexR82", 675 "Cortex-R82 ARM Processors", [ 676 FeaturePostRAScheduler, 677 // TODO: crypto and FuseAES 678 // All other features are implied by v8_0r ops: 679 HasV8_0rOps, 680 ]>; 681 682def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1", 683 "Cortex-X1 ARM processors", [ 684 HasV8_2aOps, 685 FeatureCrypto, 686 FeatureFPARMv8, 687 FeatureFuseAES, 688 FeatureNEON, 689 FeatureRCPC, 690 FeaturePerfMon, 691 FeaturePostRAScheduler, 692 FeatureSPE, 693 FeatureFullFP16, 694 FeatureDotProd]>; 695 696def ProcA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX", 697 "Fujitsu A64FX processors", [ 698 HasV8_2aOps, 699 FeatureFPARMv8, 700 FeatureNEON, 701 FeatureSHA2, 702 FeaturePerfMon, 703 FeatureFullFP16, 704 FeatureSVE, 705 FeaturePostRAScheduler, 706 FeatureComplxNum 707 ]>; 708 709def ProcCarmel : SubtargetFeature<"carmel", "ARMProcFamily", "Carmel", 710 "Nvidia Carmel processors", [ 711 HasV8_2aOps, 712 FeatureNEON, 713 FeatureCrypto, 714 FeatureFullFP16 715 ]>; 716 717// Note that cyclone does not fuse AES instructions, but newer apple chips do 718// perform the fusion and cyclone is used by default when targetting apple OSes. 719def ProcAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7", 720 "Apple A7 (the CPU formerly known as Cyclone)", [ 721 FeatureAlternateSExtLoadCVTF32Pattern, 722 FeatureArithmeticBccFusion, 723 FeatureArithmeticCbzFusion, 724 FeatureCrypto, 725 FeatureDisableLatencySchedHeuristic, 726 FeatureFPARMv8, 727 FeatureFuseAES, 728 FeatureFuseCryptoEOR, 729 FeatureNEON, 730 FeaturePerfMon, 731 FeatureZCRegMove, 732 FeatureZCZeroing, 733 FeatureZCZeroingFPWorkaround 734 ]>; 735 736def ProcAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10", 737 "Apple A10", [ 738 FeatureAlternateSExtLoadCVTF32Pattern, 739 FeatureArithmeticBccFusion, 740 FeatureArithmeticCbzFusion, 741 FeatureCrypto, 742 FeatureDisableLatencySchedHeuristic, 743 FeatureFPARMv8, 744 FeatureFuseAES, 745 FeatureFuseCryptoEOR, 746 FeatureNEON, 747 FeaturePerfMon, 748 FeatureZCRegMove, 749 FeatureZCZeroing, 750 FeatureCRC, 751 FeatureRDM, 752 FeaturePAN, 753 FeatureLOR, 754 FeatureVH, 755 ]>; 756 757def ProcAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11", 758 "Apple A11", [ 759 FeatureAlternateSExtLoadCVTF32Pattern, 760 FeatureArithmeticBccFusion, 761 FeatureArithmeticCbzFusion, 762 FeatureCrypto, 763 FeatureDisableLatencySchedHeuristic, 764 FeatureFPARMv8, 765 FeatureFuseAES, 766 FeatureFuseCryptoEOR, 767 FeatureNEON, 768 FeaturePerfMon, 769 FeatureZCRegMove, 770 FeatureZCZeroing, 771 FeatureFullFP16, 772 HasV8_2aOps 773 ]>; 774 775def ProcAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12", 776 "Apple A12", [ 777 FeatureAlternateSExtLoadCVTF32Pattern, 778 FeatureArithmeticBccFusion, 779 FeatureArithmeticCbzFusion, 780 FeatureCrypto, 781 FeatureDisableLatencySchedHeuristic, 782 FeatureFPARMv8, 783 FeatureFuseAES, 784 FeatureFuseCryptoEOR, 785 FeatureNEON, 786 FeaturePerfMon, 787 FeatureZCRegMove, 788 FeatureZCZeroing, 789 FeatureFullFP16, 790 HasV8_3aOps 791 ]>; 792 793def ProcAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13", 794 "Apple A13", [ 795 FeatureAlternateSExtLoadCVTF32Pattern, 796 FeatureArithmeticBccFusion, 797 FeatureArithmeticCbzFusion, 798 FeatureCrypto, 799 FeatureDisableLatencySchedHeuristic, 800 FeatureFPARMv8, 801 FeatureFuseAES, 802 FeatureFuseCryptoEOR, 803 FeatureNEON, 804 FeaturePerfMon, 805 FeatureZCRegMove, 806 FeatureZCZeroing, 807 FeatureFullFP16, 808 FeatureFP16FML, 809 FeatureSHA3, 810 HasV8_4aOps 811 ]>; 812 813def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3", 814 "Samsung Exynos-M3 processors", 815 [FeatureCRC, 816 FeatureCrypto, 817 FeatureExynosCheapAsMoveHandling, 818 FeatureForce32BitJumpTables, 819 FeatureFuseAddress, 820 FeatureFuseAES, 821 FeatureFuseCCSelect, 822 FeatureFuseLiterals, 823 FeatureLSLFast, 824 FeaturePerfMon, 825 FeaturePostRAScheduler, 826 FeaturePredictableSelectIsExpensive, 827 FeatureZCZeroingFP]>; 828 829def ProcExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3", 830 "Samsung Exynos-M4 processors", 831 [HasV8_2aOps, 832 FeatureArithmeticBccFusion, 833 FeatureArithmeticCbzFusion, 834 FeatureCrypto, 835 FeatureDotProd, 836 FeatureExynosCheapAsMoveHandling, 837 FeatureForce32BitJumpTables, 838 FeatureFullFP16, 839 FeatureFuseAddress, 840 FeatureFuseAES, 841 FeatureFuseArithmeticLogic, 842 FeatureFuseCCSelect, 843 FeatureFuseLiterals, 844 FeatureLSLFast, 845 FeaturePerfMon, 846 FeaturePostRAScheduler, 847 FeatureZCZeroing]>; 848 849def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", 850 "Qualcomm Kryo processors", [ 851 FeatureCRC, 852 FeatureCrypto, 853 FeatureCustomCheapAsMoveHandling, 854 FeatureFPARMv8, 855 FeatureNEON, 856 FeaturePerfMon, 857 FeaturePostRAScheduler, 858 FeaturePredictableSelectIsExpensive, 859 FeatureZCZeroing, 860 FeatureLSLFast 861 ]>; 862 863def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor", 864 "Qualcomm Falkor processors", [ 865 FeatureCRC, 866 FeatureCrypto, 867 FeatureCustomCheapAsMoveHandling, 868 FeatureFPARMv8, 869 FeatureNEON, 870 FeaturePerfMon, 871 FeaturePostRAScheduler, 872 FeaturePredictableSelectIsExpensive, 873 FeatureRDM, 874 FeatureZCZeroing, 875 FeatureLSLFast, 876 FeatureSlowSTRQro 877 ]>; 878 879def ProcNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily", 880 "NeoverseE1", 881 "Neoverse E1 ARM processors", [ 882 HasV8_2aOps, 883 FeatureCrypto, 884 FeatureDotProd, 885 FeatureFPARMv8, 886 FeatureFullFP16, 887 FeatureNEON, 888 FeatureRCPC, 889 FeatureSSBS, 890 ]>; 891 892def ProcNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", 893 "NeoverseN1", 894 "Neoverse N1 ARM processors", [ 895 HasV8_2aOps, 896 FeatureCrypto, 897 FeatureDotProd, 898 FeatureFPARMv8, 899 FeatureFullFP16, 900 FeatureNEON, 901 FeatureRCPC, 902 FeatureSPE, 903 FeatureSSBS, 904 ]>; 905 906def ProcNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", 907 "NeoverseN2", 908 "Neoverse N2 ARM processors", [ 909 HasV8_5aOps, 910 FeatureBF16, 911 FeatureETE, 912 FeatureMatMulInt8, 913 FeatureMTE, 914 FeatureSVE2, 915 FeatureSVE2BitPerm, 916 FeatureTRBE]>; 917 918def ProcNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", 919 "NeoverseV1", 920 "Neoverse V1 ARM processors", [ 921 HasV8_4aOps, 922 FeatureBF16, 923 FeatureCacheDeepPersist, 924 FeatureCrypto, 925 FeatureFPARMv8, 926 FeatureFP16FML, 927 FeatureFullFP16, 928 FeatureFuseAES, 929 FeatureMatMulInt8, 930 FeatureNEON, 931 FeaturePerfMon, 932 FeaturePostRAScheduler, 933 FeatureRandGen, 934 FeatureSPE, 935 FeatureSSBS, 936 FeatureSVE]>; 937 938def ProcSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", 939 "Qualcomm Saphira processors", [ 940 FeatureCrypto, 941 FeatureCustomCheapAsMoveHandling, 942 FeatureFPARMv8, 943 FeatureNEON, 944 FeatureSPE, 945 FeaturePerfMon, 946 FeaturePostRAScheduler, 947 FeaturePredictableSelectIsExpensive, 948 FeatureZCZeroing, 949 FeatureLSLFast, 950 HasV8_4aOps]>; 951 952def ProcThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily", 953 "ThunderX2T99", 954 "Cavium ThunderX2 processors", [ 955 FeatureAggressiveFMA, 956 FeatureCRC, 957 FeatureCrypto, 958 FeatureFPARMv8, 959 FeatureArithmeticBccFusion, 960 FeatureNEON, 961 FeaturePostRAScheduler, 962 FeaturePredictableSelectIsExpensive, 963 FeatureLSE, 964 HasV8_1aOps]>; 965 966def ProcThunderX3T110 : SubtargetFeature<"thunderx3t110", "ARMProcFamily", 967 "ThunderX3T110", 968 "Marvell ThunderX3 processors", [ 969 FeatureAggressiveFMA, 970 FeatureCRC, 971 FeatureCrypto, 972 FeatureFPARMv8, 973 FeatureArithmeticBccFusion, 974 FeatureNEON, 975 FeaturePostRAScheduler, 976 FeaturePredictableSelectIsExpensive, 977 FeatureLSE, 978 FeaturePA, 979 FeatureUseAA, 980 FeatureBalanceFPOps, 981 FeaturePerfMon, 982 FeatureStrictAlign, 983 HasV8_3aOps]>; 984 985def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX", 986 "Cavium ThunderX processors", [ 987 FeatureCRC, 988 FeatureCrypto, 989 FeatureFPARMv8, 990 FeaturePerfMon, 991 FeaturePostRAScheduler, 992 FeaturePredictableSelectIsExpensive, 993 FeatureNEON]>; 994 995def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily", 996 "ThunderXT88", 997 "Cavium ThunderX processors", [ 998 FeatureCRC, 999 FeatureCrypto, 1000 FeatureFPARMv8, 1001 FeaturePerfMon, 1002 FeaturePostRAScheduler, 1003 FeaturePredictableSelectIsExpensive, 1004 FeatureNEON]>; 1005 1006def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily", 1007 "ThunderXT81", 1008 "Cavium ThunderX processors", [ 1009 FeatureCRC, 1010 FeatureCrypto, 1011 FeatureFPARMv8, 1012 FeaturePerfMon, 1013 FeaturePostRAScheduler, 1014 FeaturePredictableSelectIsExpensive, 1015 FeatureNEON]>; 1016 1017def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily", 1018 "ThunderXT83", 1019 "Cavium ThunderX processors", [ 1020 FeatureCRC, 1021 FeatureCrypto, 1022 FeatureFPARMv8, 1023 FeaturePerfMon, 1024 FeaturePostRAScheduler, 1025 FeaturePredictableSelectIsExpensive, 1026 FeatureNEON]>; 1027 1028def ProcTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110", 1029 "HiSilicon TS-V110 processors", [ 1030 HasV8_2aOps, 1031 FeatureCrypto, 1032 FeatureCustomCheapAsMoveHandling, 1033 FeatureFPARMv8, 1034 FeatureFuseAES, 1035 FeatureNEON, 1036 FeaturePerfMon, 1037 FeaturePostRAScheduler, 1038 FeatureSPE, 1039 FeatureFullFP16, 1040 FeatureFP16FML, 1041 FeatureDotProd]>; 1042 1043def : ProcessorModel<"generic", NoSchedModel, [ 1044 FeatureFPARMv8, 1045 FeatureFuseAES, 1046 FeatureNEON, 1047 FeaturePerfMon, 1048 FeaturePostRAScheduler, 1049// ETE and TRBE are future architecture extensions. We temporarily enable them 1050// by default for users targeting generic AArch64, until it is decided in which 1051// armv8.x-a architecture revision they will end up. The extensions do not 1052// affect code generated by the compiler and can be used only by explicitly 1053// mentioning the new system register names in assembly. 1054 FeatureETE 1055 ]>; 1056 1057def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>; 1058def : ProcessorModel<"cortex-a34", CortexA53Model, [ProcA35]>; 1059def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>; 1060def : ProcessorModel<"cortex-a55", CortexA55Model, [ProcA55]>; 1061def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>; 1062def : ProcessorModel<"cortex-a65", CortexA53Model, [ProcA65]>; 1063def : ProcessorModel<"cortex-a65ae", CortexA53Model, [ProcA65]>; 1064def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>; 1065def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>; 1066def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>; 1067def : ProcessorModel<"cortex-a76", CortexA57Model, [ProcA76]>; 1068def : ProcessorModel<"cortex-a76ae", CortexA57Model, [ProcA76]>; 1069def : ProcessorModel<"cortex-a77", CortexA57Model, [ProcA77]>; 1070def : ProcessorModel<"cortex-a78", CortexA57Model, [ProcA78]>; 1071def : ProcessorModel<"cortex-r82", CortexA55Model, [ProcR82]>; 1072def : ProcessorModel<"cortex-x1", CortexA57Model, [ProcX1]>; 1073def : ProcessorModel<"neoverse-e1", CortexA53Model, [ProcNeoverseE1]>; 1074def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>; 1075def : ProcessorModel<"neoverse-n2", CortexA57Model, [ProcNeoverseN2]>; 1076def : ProcessorModel<"neoverse-v1", CortexA57Model, [ProcNeoverseV1]>; 1077def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>; 1078def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>; 1079def : ProcessorModel<"exynos-m5", ExynosM5Model, [ProcExynosM4]>; 1080def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>; 1081def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>; 1082def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>; 1083// Cavium ThunderX/ThunderX T8X Processors 1084def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>; 1085def : ProcessorModel<"thunderxt88", ThunderXT8XModel, [ProcThunderXT88]>; 1086def : ProcessorModel<"thunderxt81", ThunderXT8XModel, [ProcThunderXT81]>; 1087def : ProcessorModel<"thunderxt83", ThunderXT8XModel, [ProcThunderXT83]>; 1088// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan. 1089def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>; 1090// Marvell ThunderX3T110 Processors. 1091def : ProcessorModel<"thunderx3t110", ThunderX3T110Model, [ProcThunderX3T110]>; 1092def : ProcessorModel<"tsv110", TSV110Model, [ProcTSV110]>; 1093 1094// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode. 1095def : ProcessorModel<"cyclone", CycloneModel, [ProcAppleA7]>; 1096 1097// iPhone and iPad CPUs 1098def : ProcessorModel<"apple-a7", CycloneModel, [ProcAppleA7]>; 1099def : ProcessorModel<"apple-a8", CycloneModel, [ProcAppleA7]>; 1100def : ProcessorModel<"apple-a9", CycloneModel, [ProcAppleA7]>; 1101def : ProcessorModel<"apple-a10", CycloneModel, [ProcAppleA10]>; 1102def : ProcessorModel<"apple-a11", CycloneModel, [ProcAppleA11]>; 1103def : ProcessorModel<"apple-a12", CycloneModel, [ProcAppleA12]>; 1104def : ProcessorModel<"apple-a13", CycloneModel, [ProcAppleA13]>; 1105 1106// watch CPUs. 1107def : ProcessorModel<"apple-s4", CycloneModel, [ProcAppleA12]>; 1108def : ProcessorModel<"apple-s5", CycloneModel, [ProcAppleA12]>; 1109 1110// Alias for the latest Apple processor model supported by LLVM. 1111def : ProcessorModel<"apple-latest", CycloneModel, [ProcAppleA13]>; 1112 1113// Fujitsu A64FX 1114// FIXME: Scheduling model is not implemented yet. 1115def : ProcessorModel<"a64fx", NoSchedModel, [ProcA64FX]>; 1116 1117// Nvidia Carmel 1118def : ProcessorModel<"carmel", NoSchedModel, [ProcCarmel]>; 1119 1120//===----------------------------------------------------------------------===// 1121// Assembly parser 1122//===----------------------------------------------------------------------===// 1123 1124def GenericAsmParserVariant : AsmParserVariant { 1125 int Variant = 0; 1126 string Name = "generic"; 1127 string BreakCharacters = "."; 1128 string TokenizingCharacters = "[]*!/"; 1129} 1130 1131def AppleAsmParserVariant : AsmParserVariant { 1132 int Variant = 1; 1133 string Name = "apple-neon"; 1134 string BreakCharacters = "."; 1135 string TokenizingCharacters = "[]*!/"; 1136} 1137 1138//===----------------------------------------------------------------------===// 1139// Assembly printer 1140//===----------------------------------------------------------------------===// 1141// AArch64 Uses the MC printer for asm output, so make sure the TableGen 1142// AsmWriter bits get associated with the correct class. 1143def GenericAsmWriter : AsmWriter { 1144 string AsmWriterClassName = "InstPrinter"; 1145 int PassSubtarget = 1; 1146 int Variant = 0; 1147 bit isMCAsmWriter = 1; 1148} 1149 1150def AppleAsmWriter : AsmWriter { 1151 let AsmWriterClassName = "AppleInstPrinter"; 1152 int PassSubtarget = 1; 1153 int Variant = 1; 1154 int isMCAsmWriter = 1; 1155} 1156 1157//===----------------------------------------------------------------------===// 1158// Target Declaration 1159//===----------------------------------------------------------------------===// 1160 1161def AArch64 : Target { 1162 let InstructionSet = AArch64InstrInfo; 1163 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant]; 1164 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter]; 1165 let AllowRegisterRenaming = 1; 1166} 1167 1168//===----------------------------------------------------------------------===// 1169// Pfm Counters 1170//===----------------------------------------------------------------------===// 1171 1172include "AArch64PfmCounters.td" 1173