| /external/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenHwModes.h | 28 struct HwMode { struct
29 HwMode(Record *R);
48 const HwMode &getMode(unsigned Id) const { in getMode() argument
59 std::vector<HwMode> Modes;
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| D | CodeGenHwModes.cpp | 21 HwMode::HwMode(Record *R) { in HwMode() function in HwMode
27 void HwMode::dump() const { in dump()
96 for (const HwMode &M : Modes) { in dump()
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| D | CodeEmitterGen.cpp | 59 CodeGenTarget &Target, int HwMode = -1);
349 CodeGenTarget &Target, int HwMode) { in emitInstructionBaseValues() argument
351 if (HwMode == -1) in emitInstructionBaseValues()
354 o << " static const uint64_t InstBits_" << HWM.getMode(HwMode).Name in emitInstructionBaseValues()
370 if (EBM.hasMode(HwMode)) in emitInstructionBaseValues()
371 EncodingDef = EBM.get(HwMode); in emitInstructionBaseValues()
444 for (unsigned HwMode : HwModes) in run() local
445 emitInstructionBaseValues(o, NumberedInstructions, Target, (int)HwMode); in run()
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| D | SubtargetEmitter.cpp | 1689 const HwMode &HM = CGH.getMode(M); in EmitHwModeCheck()
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| /external/llvm-project/llvm/test/TableGen/ |
| D | HwModeEncodeDecode.td | 16 def ModeA : HwMode<"+a">;
17 def ModeB : HwMode<"+b">;
88 // ENCODER: switch (HwMode) {
89 // ENCODER: default: llvm_unreachable("Unhandled HwMode");
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| D | HwModeSelect.td | 21 def TestMode1 : HwMode<"+feat1">;
22 def TestMode2 : HwMode<"+feat2">;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVRegisterInfo.cpp | 38 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode) in RISCVRegisterInfo() argument
40 /*PC*/0, HwMode) {} in RISCVRegisterInfo()
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| D | RISCV.td | 67 def RV64 : HwMode<"+64bit">;
68 def RV32 : HwMode<"-64bit">;
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| D | RISCVRegisterInfo.h | 25 RISCVRegisterInfo(unsigned HwMode);
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVRegisterInfo.cpp | 44 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode) in RISCVRegisterInfo() argument
46 /*PC*/0, HwMode) {} in RISCVRegisterInfo()
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| D | RISCVRegisterInfo.h | 25 RISCVRegisterInfo(unsigned HwMode);
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| D | RISCV.td | 193 def RV64 : HwMode<"+64bit">;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.h | 31 HexagonRegisterInfo(unsigned HwMode);
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| D | HexagonRegisterInfo.cpp | 44 HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode) in HexagonRegisterInfo() argument
46 0/*PC*/, HwMode) {} in HexagonRegisterInfo()
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| D | Hexagon.td | 95 def Hvx64: HwMode<"+hvx-length64b">;
96 def Hvx128: HwMode<"+hvx-length128b">;
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.h | 31 HexagonRegisterInfo(unsigned HwMode);
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| D | HexagonRegisterInfo.cpp | 44 HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode) in HexagonRegisterInfo() argument
46 0/*PC*/, HwMode) {} in HexagonRegisterInfo()
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| D | Hexagon.td | 126 def Hvx64: HwMode<"+hvx-length64b">;
127 def Hvx128: HwMode<"+hvx-length128b">;
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 245 unsigned HwMode; variable
654 return RCInfos[getNumRegClasses() * HwMode + RC.getID()]; in getRegClassInfo()
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 245 unsigned HwMode; variable
673 return RCInfos[getNumRegClasses() * HwMode + RC.getID()]; in getRegClassInfo()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | Target.td | 23 class HwMode<string FS> {
36 def DefaultMode : HwMode<"">;
43 class HwModeSelect<list<HwMode> Ms> {
44 list<HwMode> Modes = Ms;
52 class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts>
67 class RegInfoByHwMode<list<HwMode> Ms = [], list<RegInfo> Ts = []>
446 // Allows specifying an InstructionEncoding by HwMode. If an Instruction specifies
448 // to encode and decode based on HwMode.
449 class EncodingByHwMode<list<HwMode> Ms = [], list<InstructionEncoding> Ts = []>
466 // Allows specifying a canonical InstructionEncoding by HwMode. If non-empty,
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| /external/llvm-project/llvm/include/llvm/Target/ |
| D | Target.td | 23 class HwMode<string FS> {
36 def DefaultMode : HwMode<"">;
43 class HwModeSelect<list<HwMode> Ms> {
44 list<HwMode> Modes = Ms;
52 class ValueTypeByHwMode<list<HwMode> Ms, list<ValueType> Ts>
67 class RegInfoByHwMode<list<HwMode> Ms = [], list<RegInfo> Ts = []>
458 // Allows specifying an InstructionEncoding by HwMode. If an Instruction specifies
460 // to encode and decode based on HwMode.
461 class EncodingByHwMode<list<HwMode> Ms = [], list<InstructionEncoding> Ts = []>
478 // Allows specifying a canonical InstructionEncoding by HwMode. If non-empty,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 53 RCInfos(RCIs), HwMode(Mode) { in TargetRegisterInfo()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 62 RCInfos(RCIs), HwMode(Mode) { in TargetRegisterInfo()
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenRegisterInfo.inc | 3843 unsigned PC = 0, unsigned HwMode = 0);
5679 unsigned PC, unsigned HwMode)
5682 LaneBitmask(0xFFFFFFC0), RegClassInfos, HwMode) {
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