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Searched refs:LXSD (Results 1 – 19 of 19) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dscheduling-mem-dependency.ll22 ; LXSD is an instruction that can be modeled.
54 ; CHECK-P9:SU({{[0-9]+}}): renamable $vf{{[0-9]+}} = LXSD 136
55 ; CHECK-P9:SU({{[0-9]+}}): renamable $vf{{[0-9]+}} = LXSD 696
56 ; CHECK-P9:SU({{[0-9]+}}): renamable $vf{{[0-9]+}} = LXSD 776
57 ; CHECK-P9:SU({{[0-9]+}}): renamable $vf{{[0-9]+}} = LXSD 616
/external/llvm-project/lld/ELF/Arch/
DPPCInsns.def14 PCREL_OPT(LXSD, PLXSD, ONLY_RST);
DPPC64.cpp79 LXSD = 0xe4000002, enumerator
441 case PPCLegacyInsn::LXSD: in isDSFormInstruction()
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCPreEmitPeephole.cpp74 case PPC::LXSD: in hasPCRelativeForm()
DPPCRegisterInfo.cpp125 ImmToIdxMap[PPC::LXSD] = PPC::LXSDX; in PPCRegisterInfo()
1098 case PPC::LXSD: in offsetMinAlignForOpcode()
DP9InstrResources.td723 LXSD,
DPPCInstrInfo.cpp2473 UpperOpcode = PPC::LXSD; in expandVSXMemPseudo()
3796 III.ImmOpcode = PPC::LXSD; in instrHasImmForm()
DPPCInstrVSX.td1674 def LXSD : DSForm_1<57, 2, (outs vfrc:$vD), (ins memrix:$src),
3778 (f128 (XSCVSDQP (LXSD iaddrX4:$src)))>;
3782 (f128 (XSCVUDQP (LXSD iaddrX4:$src)))>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp110 ImmToIdxMap[PPC::LXSD] = PPC::LXSDX; in PPCRegisterInfo()
977 case PPC::LXSD: in offsetMinAlignForOpcode()
DPPCInstrInfo.cpp2058 UpperOpcode = PPC::LXSD; in expandVSXMemPseudo()
3363 III.ImmOpcode = PPC::LXSD; in instrHasImmForm()
DP9InstrResources.td722 LXSD,
DPPCInstrVSX.td3020 def LXSD : DSForm_1<57, 2, (outs vfrc:$vD), (ins memrix:$src),
3692 (f128 (XSCVSDQP (LXSD iaddrX4:$src)))>;
3696 (f128 (XSCVUDQP (LXSD iaddrX4:$src)))>;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenMCCodeEmitter.inc1128 UINT64_C(3825205250), // LXSD
4497 case PPC::LXSD:
7538 CEFBS_None, // LXSD = 1115
DPPCGenAsmWriter.inc2783 33574730U, // LXSD
5074 0U, // LXSD
DPPCGenDisassemblerTables.inc2359 /* 10988 */ MCD::OPC_Decode, 219, 8, 123, // Opcode: LXSD
DPPCGenInstrInfo.inc1130 LXSD = 1115,
4099 …ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #1115 = LXSD
DPPCGenAsmMatcher.inc5821 …{ 6577 /* lxsd */, PPC::LXSD, Convert__RegVFRC1_0__DispRIX1_1__RegGxRCNoR01_2, AMFBS_None, { MCK_R…
DPPCGenDAGISel.inc34720 /* 89375*/ OPC_EmitNode1, TARGET_VAL(PPC::LXSD), 0|OPFL_Chain|OPFL_MemRefs,
34725 // Dst: (XSCVUDQP:{ *:[f128] } (LXSD:{ *:[f64] } iaddrX4:{ *:[iPTR] }:$src))
35162 /* 90293*/ OPC_EmitNode1, TARGET_VAL(PPC::LXSD), 0|OPFL_Chain|OPFL_MemRefs,
35167 // Dst: (XSCVSDQP:{ *:[f128] } (LXSD:{ *:[f64] } iaddrX4:{ *:[iPTR] }:$src))
/external/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td2123 def LXSD : DSForm_1<57, 2, (outs vrrc:$vD), (ins memrix:$src),