Home
last modified time | relevance | path

Searched refs:MRM5r (Results 1 – 25 of 33) sorted by relevance

12

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrShiftRotate.td123 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
126 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
129 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
132 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
137 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$src2),
140 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
144 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
148 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$src2),
153 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
156 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrFPStack.td326 def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t{$op, %st|st, $op}">;
327 def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st, $op|$op, st}">;
328 def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t{%st, $op|$op, st}">;
680 def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop
687 def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i)
689 def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop
DX86InstrSystem.td349 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable;
456 def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
458 def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
DX86InstrArithmetic.td111 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>,
115 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
119 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>,
123 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>,
1181 defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m,
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td126 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
129 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
132 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
135 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
140 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$src2),
143 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
147 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
151 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$src2),
156 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
159 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrFPStack.td271 def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t$op">;
272 def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st(0), $op|$op, st(0)}">;
273 def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t$op">;
591 def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop
598 def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i)
600 def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop
DX86InstrArithmetic.td113 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", [],
117 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", [],
121 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", [],
125 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", [],
1200 defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m,
DX86InstrSystem.td382 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h296 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 enumerator
687 case X86II::MRM4r: case X86II::MRM5r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp871 case X86II::MRM4r: case X86II::MRM5r: in EmitVEXOpcodePrefix()
1022 case X86II::MRM4r: case X86II::MRM5r: in DetermineREXPrefix()
1357 case X86II::MRM4r: case X86II::MRM5r: in encodeInstruction()
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrShiftRotate.td123 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
126 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
129 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
132 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
137 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$src2),
140 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
144 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
148 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$src2),
153 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
156 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrFPStack.td320 def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t{$op, %st|st, $op}">;
321 def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st, $op|$op, st}">;
322 def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t{%st, $op|$op, st}">;
677 def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop
684 def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i)
686 def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop
DX86InstrSystem.td359 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg), "verw\t$seg", []>, TB, NotMemoryFoldable;
466 def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
468 def INCSSPQ : RI<0xAE, MRM5r, (outs), (ins GR64:$src), "incsspq\t$src",
DX86InstrArithmetic.td111 def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", []>,
115 def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
119 def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>,
123 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>,
1181 defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m,
/external/llvm-project/llvm/utils/TableGen/
DX86RecognizableInstr.h124 MRM4r = 52, MRM5r = 53, MRM6r = 54, MRM7r = 55, enumerator
DX86RecognizableInstr.cpp659 case X86Local::MRM5r: in emitInstructionSpecifier()
796 case X86Local::MRM4r: case X86Local::MRM5r: in emitDecodePath()
DX86FoldTablesEmitter.cpp434 (MemFormNum == X86Local::MRM5m && RegFormNum == X86Local::MRM5r) || in areOppositeForms()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h667 MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, // Format /4 /5 /6 /7 enumerator
1057 case X86II::MRM4r: case X86II::MRM5r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp1089 case X86II::MRM5r: in emitVEXOpcodePrefix()
1244 case X86II::MRM5r: in determineREXPrefix()
1633 case X86II::MRM5r: in encodeInstruction()
/external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h718 MRM4r = 52, MRM5r = 53, MRM6r = 54, MRM7r = 55, // Format /4 /5 /6 /7 enumerator
1130 case X86II::MRM4r: case X86II::MRM5r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp1121 case X86II::MRM5r: in emitVEXOpcodePrefix()
1281 case X86II::MRM5r: in emitREXPrefix()
1654 case X86II::MRM5r: in encodeInstruction()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp109 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, enumerator
720 case X86Local::MRM5r: in emitInstructionSpecifier()
854 case X86Local::MRM4r: case X86Local::MRM5r: in emitDecodePath()
/external/llvm-project/llvm/test/TableGen/
DTargetInstrInfo.td53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
/external/llvm/test/TableGen/
DTargetInstrInfo.td53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
/external/llvm-project/llvm/tools/llvm-exegesis/lib/X86/
DTarget.cpp79 case X86II::MRM5r: in isInvalidMemoryInstr()

12