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Searched refs:OpNode (Results 1 – 25 of 119) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86InstrAVX512.td1354 multiclass avx512_cmp_scalar<X86VectorVTInfo _, SDNode OpNode, SDNode OpNodeRnd>{
1361 (OpNode (_.VT _.RC:$src1),
1369 (OpNode (_.VT _.RC:$src1),
1409 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1418 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1432 multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1437 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
1442 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1450 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1457 (OpNode (_.VT _.RC:$src1),
[all …]
DX86InstrXOP.td86 multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode,
92 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
98 (vt128 (OpNode (vt128 VR128:$src1),
105 (vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))),
125 multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
131 (vt128 (OpNode (vt128 VR128:$src1), imm:$src2)))]>, XOP;
136 (vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))), imm:$src2)))]>, XOP;
180 multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128> {
187 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
195 (vt128 (OpNode (vt128 VR128:$src1),
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DX86InstrFMA.td145 SDPatternOperator OpNode = null_frag> {
151 [(set RC:$dst, (OpNode RC:$src2, RC:$src1, RC:$src3))]>;
159 (OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>;
195 SDNode OpNode, RegisterClass RC,
199 OpNode>;
225 SDNode OpNode> {
227 defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", OpNode,
232 defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", OpNode,
268 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode,
276 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, MemOp4;
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/external/llvm-project/llvm/lib/Target/VE/
DVVPInstrPatternsVec.td21 SDPatternOperator OpNode,
26 def : Pat<(OpNode
31 def : Pat<(OpNode DataVT:$vx, DataVT:$vy, (MaskVT true_mask), i32:$avl),
36 def : Pat<(OpNode
41 def : Pat<(OpNode DataVT:$vx, DataVT:$vy, MaskVT:$mask, i32:$avl),
54 SDPatternOperator OpNode,
57 defm : VectorBinaryArith<OpNode,
60 defm : VectorBinaryArith<OpNode,
/external/tensorflow/tensorflow/core/profiler/internal/
Dtfprof_op.h55 int64 SearchRoot(const std::vector<OpNode*> nodes,
67 string FormatNode(OpNode* node, OpNode* root, const Options& opts) const;
71 std::unique_ptr<OpNode> root_;
72 std::map<string, std::unique_ptr<OpNode>> cnodes_map_;
Dtfprof_op.cc94 std::unique_ptr<OpNode>(new OpNode(tn.second.get())); in Build()
99 root_.reset(new OpNode(tfcnodes_map_[kTFProfRoot].get())); in Build()
122 std::vector<OpNode*> nodes; in ShowInternal()
131 OpNode* pre = nullptr; in ShowInternal()
132 std::vector<OpNode*> account_nodes; in ShowInternal()
147 std::vector<OpNode*> show_nodes; in ShowInternal()
150 OpNode* n = account_nodes[i]; in ShowInternal()
175 for (OpNode* node : show_nodes) { in ShowInternal()
192 int64 TFOp::SearchRoot(const std::vector<OpNode*> nodes, in SearchRoot()
222 string TFOp::FormatNode(OpNode* node, OpNode* root, const Options& opts) const { in FormatNode()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.h80 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
82 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
84 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
87 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
89 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
91 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td1327 SDNode OpNode>
1329 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1332 SDNode OpNode>
1334 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1340 SDNode OpNode, SDNode OpNode_setflags> {
1341 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1345 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1364 SDPatternOperator OpNode>
1367 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1380 SDPatternOperator OpNode>
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td1805 SDPatternOperator OpNode>
1808 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>,
1866 SDNode OpNode>
1868 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1871 SDNode OpNode>
1873 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1879 SDNode OpNode, SDNode OpNode_setflags> {
1880 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1884 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1903 SDPatternOperator OpNode,
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/external/llvm-project/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.h85 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
87 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
89 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
91 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
93 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
95 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
DNVPTXInstrInfo.td166 multiclass I3<string OpcStr, SDNode OpNode> {
170 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, Int64Regs:$b))]>;
174 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
178 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
182 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
186 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, Int16Regs:$b))]>;
190 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
195 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
199 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
203 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.h85 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
87 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
89 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
91 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
93 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
95 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
DNVPTXInstrInfo.td166 multiclass I3<string OpcStr, SDNode OpNode> {
170 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, Int64Regs:$b))]>;
174 [(set Int64Regs:$dst, (OpNode Int64Regs:$a, imm:$b))]>;
178 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
182 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
186 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, Int16Regs:$b))]>;
190 [(set Int16Regs:$dst, (OpNode Int16Regs:$a, (imm):$b))]>;
195 multiclass ADD_SUB_INT_32<string OpcStr, SDNode OpNode> {
199 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, Int32Regs:$b))]>;
203 [(set Int32Regs:$dst, (OpNode Int32Regs:$a, imm:$b))]>;
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/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td1931 SDPatternOperator OpNode>
1934 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>,
2002 SDNode OpNode>
2004 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
2007 SDNode OpNode>
2009 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
2015 SDNode OpNode, SDNode OpNode_setflags> {
2016 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
2020 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
2039 SDPatternOperator OpNode,
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrAVX512.td1268 X86VectorVTInfo _, SDPatternOperator OpNode,
1274 (_.VT (OpNode SrcRC:$src))>, T8PD, EVEX,
1279 X86VectorVTInfo _, SDPatternOperator OpNode,
1289 def : Pat <(_.VT (OpNode SrcRC:$src)),
1293 def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.RC:$src0),
1297 def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.ImmAllZerosV),
1303 AVX512VLVectorVTInfo _, SDPatternOperator OpNode,
1307 OpNode, SrcRC, Subreg>, EVEX_V512;
1310 _.info256, OpNode, SrcRC, Subreg>, EVEX_V256;
1312 _.info128, OpNode, SrcRC, Subreg>, EVEX_V128;
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrAVX512.td1311 X86VectorVTInfo _, SDPatternOperator OpNode,
1318 (_.VT (OpNode SrcRC:$src)), /*IsCommutable*/0,
1324 X86VectorVTInfo _, SDPatternOperator OpNode,
1334 def : Pat <(_.VT (OpNode SrcRC:$src)),
1339 def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.RC:$src0),
1343 def : Pat <(vselect _.KRCWM:$mask, (_.VT (OpNode SrcRC:$src)), _.ImmAllZerosV),
1349 AVX512VLVectorVTInfo _, SDPatternOperator OpNode,
1353 OpNode, SrcRC, Subreg>, EVEX_V512;
1356 _.info256, OpNode, SrcRC, Subreg>, EVEX_V256;
1358 _.info128, OpNode, SrcRC, Subreg>, EVEX_V128;
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/external/tensorflow/tensorflow/lite/delegates/flex/
Dkernel.cc65 struct OpNode;
70 OpNode* node;
187 class OpNode { class
189 OpNode(const TfLiteIntArray* inputs, const TfLiteIntArray* outputs) in OpNode() function in tflite::flex::OpNode
191 ~OpNode() { in ~OpNode()
316 OpNode(const OpNode&) = delete;
317 OpNode& operator=(const OpNode&) = delete;
338 OpNode* node_data) { in ExecuteFlexOp()
370 std::vector<std::unique_ptr<OpNode>> nodes;
406 op_data_->nodes.emplace_back(new OpNode(node->inputs, node->outputs)); in Init()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td266 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
272 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
277 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
283 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
288 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
294 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
299 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
305 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
310 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
316 list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, timmZExt5:$sa))];
[all …]
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td259 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
265 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
270 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
276 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
281 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
287 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
292 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
298 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
303 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
309 list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, immZExt5:$sa))];
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DMipsInstrFPU.td105 SDPatternOperator OpNode= null_frag> :
108 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
114 SDPatternOperator OpNode = null_frag> {
115 def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
116 def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
122 InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
129 SDPatternOperator OpNode= null_frag> {
130 def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
132 def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
[all …]
/external/llvm-project/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td266 class ADDU_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
272 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
277 class RADDU_W_QB_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
283 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
288 class CMP_EQ_QB_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
294 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
299 class CMP_EQ_QB_R3_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
305 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))];
310 class PRECR_SRA_PH_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
316 list<dag> Pattern = [(set ROT:$rt, (OpNode ROS:$src, ROS:$rs, timmZExt5:$sa))];
[all …]
/external/skia/src/gpu/
DGrAuditTrail.cpp48 OpNode* opNode = new OpNode(proxyID); in addOp()
60 OpNode& consumerOp = *fOpsTask[index]; in opsCombined()
67 OpNode& consumedOp = *fOpsTask[consumedIndex]; in opsCombined()
90 const OpNode* bn = fOpsTask[opsTaskID].get(); in copyOutFromOpsTask()
194 void GrAuditTrail::OpNode::toJson(SkJSONWriter& writer) const { in toJson()
/external/skqp/src/gpu/
DGrAuditTrail.cpp48 OpNode* opNode = new OpNode(proxyID); in addOp()
60 OpNode& consumerOp = *fOpList[index]; in opsCombined()
67 OpNode& consumedOp = *fOpList[consumedIndex]; in opsCombined()
90 const OpNode* bn = fOpList[opListID].get(); in copyOutFromOpList()
194 void GrAuditTrail::OpNode::toJson(SkJSONWriter& writer) const { in toJson()
/external/llvm/lib/Target/BPF/
DBPFInstrInfo.td140 class ALU_RI<bits<4> Opc, string OpcodeStr, SDNode OpNode>
143 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]> {
159 class ALU_RR<bits<4> Opc, string OpcodeStr, SDNode OpNode>
162 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]> {
178 multiclass ALU<bits<4> Opc, string OpcodeStr, SDNode OpNode> {
179 def _rr : ALU_RR<Opc, OpcodeStr, OpNode>;
180 def _ri : ALU_RI<Opc, OpcodeStr, OpNode>;
316 class STOREi64<bits<2> Opc, string OpcodeStr, PatFrag OpNode>
317 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
344 class LOADi64<bits<2> SizeOp, string OpcodeStr, PatFrag OpNode>
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/external/llvm-project/llvm/lib/Target/BPF/
DBPFInstrInfo.td265 multiclass ALU<BPFArithOp Opc, string OpcodeStr, SDNode OpNode> {
270 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
275 [(set GPR:$dst, (OpNode GPR:$src2, i64immSExt32:$imm))]>;
280 [(set GPR32:$dst, (OpNode i32:$src2, i32:$src))]>;
285 [(set GPR32:$dst, (OpNode GPR32:$src2, i32immSExt32:$imm))]>;
411 class STOREi64<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode>
412 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
437 class LOADi64<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
438 : LOAD<SizeOp, OpcodeStr, [(set i64:$dst, (OpNode ADDRri:$addr))]>;
621 class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
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