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Searched refs:RegMO (Results 1 – 8 of 8) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp44 const TargetRegisterClass &RegClass, const MachineOperand &RegMO, in constrainOperandRegClass() argument
46 Register Reg = RegMO.getReg(); in constrainOperandRegClass()
56 if (RegMO.isUse()) { in constrainOperandRegClass()
61 assert(RegMO.isDef() && "Must be a definition"); in constrainOperandRegClass()
74 const MachineOperand &RegMO, unsigned OpIdx) { in constrainOperandRegClass() argument
75 Register Reg = RegMO.getReg(); in constrainOperandRegClass()
89 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); in constrainOperandRegClass()
92 assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) && in constrainOperandRegClass()
108 RegMO, OpIdx); in constrainOperandRegClass()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp50 const TargetRegisterClass &RegClass, const MachineOperand &RegMO) { in constrainOperandRegClass() argument
51 Register Reg = RegMO.getReg(); in constrainOperandRegClass()
61 if (RegMO.isUse()) { in constrainOperandRegClass()
66 assert(RegMO.isDef() && "Must be a definition"); in constrainOperandRegClass()
73 if (!RegMO.isDef()) { in constrainOperandRegClass()
88 const MachineOperand &RegMO, unsigned OpIdx) { in constrainOperandRegClass() argument
89 Register Reg = RegMO.getReg(); in constrainOperandRegClass()
103 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); in constrainOperandRegClass()
106 assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) && in constrainOperandRegClass()
122 RegMO); in constrainOperandRegClass()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DUtils.h64 const MachineOperand &RegMO, unsigned OpIdx);
81 const MachineOperand &RegMO, unsigned OpIdx);
/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DUtils.h66 const MachineOperand &RegMO);
83 const MachineOperand &RegMO, unsigned OpIdx);
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrInfo.h150 MachineOperand *&RegMO) const;
155 bool isRegElgibleForForwarding(const MachineOperand &RegMO,
DPPCInstrInfo.cpp3494 MachineOperand *&RegMO) const { in isDefMIElgibleForForwarding()
3501 RegMO = &DefMI.getOperand(1); in isDefMIElgibleForForwarding()
3511 const MachineOperand &RegMO, const MachineInstr &DefMI, in isRegElgibleForForwarding() argument
3524 Register Reg = RegMO.getReg(); in isRegElgibleForForwarding()
3622 MachineOperand *RegMO = nullptr; in transformToImmFormFedByAdd() local
3623 if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO)) in transformToImmFormFedByAdd()
3625 assert(ImmMO && RegMO && "Imm and Reg operand must have been set"); in transformToImmFormFedByAdd()
3635 if (!isRegElgibleForForwarding(*RegMO, DefMI, MI, KillDefMI, in transformToImmFormFedByAdd()
3655 MI.getOperand(III.OpNoForForwarding).ChangeToRegister(RegMO->getReg(), in transformToImmFormFedByAdd()
3657 RegMO->isKill()); in transformToImmFormFedByAdd()
[all …]
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp3927 MachineOperand *&RegMO) const { in isDefMIElgibleForForwarding()
3934 RegMO = &DefMI.getOperand(1); in isDefMIElgibleForForwarding()
3938 if (!RegMO->isReg()) in isDefMIElgibleForForwarding()
3948 const MachineOperand &RegMO, const MachineInstr &DefMI, in isRegElgibleForForwarding() argument
3961 Register Reg = RegMO.getReg(); in isRegElgibleForForwarding()
4324 MachineOperand *RegMO = nullptr; in transformToNewImmFormFedByAdd() local
4325 if (!isDefMIElgibleForForwarding(DefMI, III, ImmMO, RegMO)) in transformToNewImmFormFedByAdd()
4327 assert(ImmMO && RegMO && "Imm and Reg operand must have been set"); in transformToNewImmFormFedByAdd()
4348 MI.getOperand(III.OpNoForForwarding).setReg(RegMO->getReg()); in transformToNewImmFormFedByAdd()
4349 MI.getOperand(III.OpNoForForwarding).setIsKill(RegMO->isKill()); in transformToNewImmFormFedByAdd()
[all …]
DPPCInstrInfo.h236 MachineOperand *&RegMO) const;
242 bool isRegElgibleForForwarding(const MachineOperand &RegMO,