| /external/llvm-project/llvm/test/Transforms/InstSimplify/ |
| D | div-by-0-guard-before-smul_ov.ll | 8 ; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE:%.*]], i…
9 ; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
21 ; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE:%.*]], i…
22 ; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
35 ; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE0:%.*]], …
36 ; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
50 ; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[…
51 ; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
65 ; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[…
66 ; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
[all …]
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| D | div-by-0-guard-before-smul_ov-not.ll | 8 ; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE:%.*]], i…
9 ; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
23 ; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE:%.*]], i…
24 ; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
39 ; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE0:%.*]], …
40 ; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
56 ; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[…
57 ; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
73 ; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[…
74 ; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
[all …]
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeSPARC_32.c | 108 FAIL_IF(push_inst(compiler, SMUL | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst))); in emit_single_op()
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| D | sljitNativeSPARC_common.c | 192 #define SMUL (OPC1(0x2) | OPC3(0x0b)) macro
852 …FAIL_IF(push_inst(compiler, (op == SLJIT_LMUL_UW ? UMUL : SMUL) | D(SLJIT_R0) | S1(SLJIT_R0) | S2(… in sljit_emit_op0()
874 FAIL_IF(push_inst(compiler, SMUL | D(SLJIT_R1) | S1(SLJIT_R0) | S2(SLJIT_R1), DR(SLJIT_R1))); in sljit_emit_op0()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 342 ADD, SUB, ADC, SBB, SMUL, enumerator
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| D | X86FastISel.cpp | 2740 BaseOpc = X86ISD::SMUL; CondOpc = X86::SETOr; break; in fastLowerIntrinsicCall()
2793 } else if (BaseOpc == X86ISD::SMUL && !ResultReg) { in fastLowerIntrinsicCall()
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| D | X86ISelLowering.cpp | 15686 Opc == X86ISD::SMUL || in isX86LogicalCmp()
15918 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; in LowerSELECT()
16562 Cond.getOpcode() == X86ISD::SMUL || in LowerBRCOND()
16628 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; in LowerBRCOND()
20517 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL; in LowerXALUO()
22206 case X86ISD::SMUL: return "X86ISD::SMUL"; in getTargetNodeName()
24621 case X86ISD::SMUL: in computeKnownBitsForTargetNode()
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| D | X86InstrInfo.td | 241 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 397 SMUL, enumerator
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| D | X86ISelDAGToDAG.cpp | 4865 case X86ISD::SMUL: in Select()
4879 ROpc = Opcode == X86ISD::SMUL ? X86::IMUL8r : X86::MUL8r; in Select()
4880 MOpc = Opcode == X86ISD::SMUL ? X86::IMUL8m : X86::MUL8m; in Select()
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| D | X86FastISel.cpp | 2920 BaseOpc = X86ISD::SMUL; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2975 } else if (BaseOpc == X86ISD::SMUL && !ResultReg) { in fastLowerIntrinsicCall()
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| D | X86InstrInfo.td | 248 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 341 ADD, SUB, ADC, SBB, SMUL, UMUL, enumerator
|
| D | X86ISelDAGToDAG.cpp | 4687 case X86ISD::SMUL: in Select()
4701 ROpc = Opcode == X86ISD::SMUL ? X86::IMUL8r : X86::MUL8r; in Select()
4702 MOpc = Opcode == X86ISD::SMUL ? X86::IMUL8m : X86::MUL8m; in Select()
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| D | X86FastISel.cpp | 2901 BaseOpc = X86ISD::SMUL; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2956 } else if (BaseOpc == X86ISD::SMUL && !ResultReg) { in fastLowerIntrinsicCall()
|
| D | X86InstrInfo.td | 255 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 743 defm SMUL : F3_12<"smul", 0b001011, smullohi, IntRegs, i32, simm13Op, IIC_iu_smul>;
|
| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 743 defm SMUL : F3_12<"smul", 0b001011, smullohi, IntRegs, i32, simm13Op, IIC_iu_smul>;
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 738 defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, simm13Op, IIC_iu_smul>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrFormats.td | 854 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
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| D | ARMInstrInfo.td | 4102 defm SMUL : AI_smul<"smul">;
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrFormats.td | 978 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
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| D | ARMInstrInfo.td | 4532 defm SMUL : AI_smul<"smul">;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrFormats.td | 972 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
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| D | ARMInstrInfo.td | 4382 defm SMUL : AI_smul<"smul">;
|