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Searched refs:SrcReg0 (Results 1 – 8 of 8) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SIMDInstrOpt.cpp430 Register SrcReg0 = MI.getOperand(1).getReg(); in optimizeVectElement() local
451 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
463 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
DAArch64InstrInfo.cpp2828 unsigned SrcReg0 = SrcReg; in storeRegPairToStackSlot() local
2831 SrcReg0 = TRI.getSubReg(SrcReg, SubIdx0); in storeRegPairToStackSlot()
2837 .addReg(SrcReg0, getKillRegState(IsKill), SubIdx0) in storeRegPairToStackSlot()
4179 Register SrcReg0 = MUL->getOperand(1).getReg(); in genFusedMultiply() local
4197 if (Register::isVirtualRegister(SrcReg0)) in genFusedMultiply()
4198 MRI.constrainRegClass(SrcReg0, RC); in genFusedMultiply()
4207 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
4213 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
4219 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
4330 Register SrcReg0 = MUL->getOperand(1).getReg(); in genMaddR() local
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SIMDInstrOpt.cpp433 Register SrcReg0 = MI.getOperand(1).getReg(); in optimizeVectElement() local
454 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
466 .addReg(SrcReg0, Src0IsKill) in optimizeVectElement()
DAArch64InstrInfo.cpp3122 Register SrcReg0 = SrcReg; in storeRegPairToStackSlot() local
3125 SrcReg0 = TRI.getSubReg(SrcReg, SubIdx0); in storeRegPairToStackSlot()
3131 .addReg(SrcReg0, getKillRegState(IsKill), SubIdx0) in storeRegPairToStackSlot()
4555 Register SrcReg0 = MUL->getOperand(1).getReg(); in genFusedMultiply() local
4573 if (Register::isVirtualRegister(SrcReg0)) in genFusedMultiply()
4574 MRI.constrainRegClass(SrcReg0, RC); in genFusedMultiply()
4583 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
4589 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
4595 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
4706 Register SrcReg0 = MUL->getOperand(1).getReg(); in genMaddR() local
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp3290 unsigned SrcReg0 = MUL->getOperand(1).getReg(); in genFusedMultiply() local
3299 if (TargetRegisterInfo::isVirtualRegister(SrcReg0)) in genFusedMultiply()
3300 MRI.constrainRegClass(SrcReg0, RC); in genFusedMultiply()
3309 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
3315 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
3321 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genFusedMultiply()
3354 unsigned SrcReg0 = MUL->getOperand(1).getReg(); in genMaddR() local
3361 if (TargetRegisterInfo::isVirtualRegister(SrcReg0)) in genMaddR()
3362 MRI.constrainRegClass(SrcReg0, RC); in genMaddR()
3370 .addReg(SrcReg0, getKillRegState(Src0IsKill)) in genMaddR()
/external/mesa3d/src/gallium/drivers/r300/compiler/
Dradeon_program_alu.c63 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1) in emit2() argument
73 fpi->U.I.SrcReg[0] = SrcReg0; in emit2()
82 struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, in emit3() argument
93 fpi->U.I.SrcReg[0] = SrcReg0; in emit3()
/external/llvm-project/llvm/lib/Target/X86/
DX86InstructionSelector.cpp1317 Register SrcReg0 = I.getOperand(1).getReg(); in selectMergeValues() local
1320 const LLT SrcTy = MRI.getType(SrcReg0); in selectMergeValues()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstructionSelector.cpp1362 Register SrcReg0 = I.getOperand(1).getReg(); in selectMergeValues() local
1365 const LLT SrcTy = MRI.getType(SrcReg0); in selectMergeValues()