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Searched refs:SubRegIndex (Results 1 – 25 of 97) sorted by relevance

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/external/llvm-project/llvm/test/TableGen/
DConcatenatedSubregs.td22 def sub0 : SubRegIndex<32>;
23 def sub1 : SubRegIndex<32, 32>;
24 def sub2 : SubRegIndex<32, 64>;
26 def ssub0 : SubRegIndex<16>;
27 def ssub1 : SubRegIndex<16, 16>;
91 // CHECK-LABEL: SubRegIndex sub0:
92 // CHECK-LABEL: SubRegIndex sub1:
93 // CHECK-LABEL: SubRegIndex sub2:
95 // CHECK: SubRegIndex ssub1_ssub2:
96 // CHECK: SubRegIndex ssub3_ssub4:
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Dambiguous-composition.td3 // CHECK-NOT: warning: SubRegIndex Test::subreg_h64 and Test::subreg_h32 compose ambiguously as Tes…
4 // CHECK: warning: SubRegIndex Test::subreg_l64 and Test::subreg_l32 compose ambiguously as Test::s…
16 def subreg_l32 : SubRegIndex<32, 0>;
17 def subreg_h32 : SubRegIndex<32, 32>;
18 def subreg_h64 : SubRegIndex<64, 64>;
19 def subreg_l64 : SubRegIndex<64, 0>;
DGlobalISelEmitterRegSequence.td17 def sub0 : SubRegIndex<16>;
18 def sub1 : SubRegIndex<16, 16>;
55 // CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/1,
57 // CHECK-NEXT: GIR_AddImm, /*InsnID*/0, /*SubRegIndex*/2,
71 // CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/1,
73 // CHECK-NEXT: GIR_AddImm, /*InsnID*/1, /*SubRegIndex*/2,
DGlobalISelEmitter-nested-subregs.td8 def lo8 : SubRegIndex<8>;
9 def hi8 : SubRegIndex<8, 8>;
10 def lo16 : SubRegIndex<16>;
11 def hi16 : SubRegIndex<16, 16>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp222 unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction() local
223 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
224 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
237 unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction() local
238 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
DSIInstructions.td834 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
837 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
841 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
844 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
850 i32, v3i32, Index, !cast<SubRegIndex>(sub#Index)
853 i32, v3i32, Index, !cast<SubRegIndex>(sub#Index)
857 f32, v3f32, Index, !cast<SubRegIndex>(sub#Index)
860 f32, v3f32, Index, !cast<SubRegIndex>(sub#Index)
866 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
869 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
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/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp222 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction() local
223 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
224 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
237 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction() local
238 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
DSIRegisterInfo.td25 def lo16 : SubRegIndex<16, 0>;
26 def hi16 : SubRegIndex<16, 16>;
29 def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
33 def sub#Index#_lo16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), lo16>;
34 def sub#Index#_hi16 : ComposedSubRegIndex<!cast<SubRegIndex>(sub#Index), hi16>;
41 SubRegIndex<!mul(Size, 32), !shl(Index, 5)> {
43 !foldl([]<SubRegIndex>, Indexes<Size>.slice, acc, cur,
44 !listconcat(acc, [!cast<SubRegIndex>(sub#!add(cur, Index))]));
56 list<SubRegIndex> ret2 = [sub0, sub1];
57 list<SubRegIndex> ret3 = [sub0, sub1, sub2];
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/external/llvm-project/llvm/test/TableGen/Common/
Dreg-with-subregs-common.td23 def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
30 SubRegIndex<!mul(Size, 32), !shl(Index, 5)> {
32 !foldl([]<SubRegIndex>, Indexes<Size>.slice, acc, cur,
33 !listconcat(acc, [!cast<SubRegIndex>(sub#!add(cur, Index))]));
/external/llvm-project/llvm/lib/Target/VE/
DVERegisterInfo.td50 def sub_i32 : SubRegIndex<32, 32>; // Low 32 bit (32..63)
51 def sub_f32 : SubRegIndex<32>; // High 32 bit (0..31)
52 def sub_even : SubRegIndex<64>; // High 64 bit (0..63)
53 def sub_odd : SubRegIndex<64, 64>; // Low 64 bit (64..127)
54 def sub_vm_even : SubRegIndex<256>; // High 256 bit (0..255)
55 def sub_vm_odd : SubRegIndex<256, 256>; // Low 256 bit (256..511)
/external/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td23 def sub_32 : SubRegIndex<32>;
25 def bsub : SubRegIndex<8>;
26 def hsub : SubRegIndex<16>;
27 def ssub : SubRegIndex<32>;
28 def dsub : SubRegIndex<32>;
29 def sube32 : SubRegIndex<32>;
30 def subo32 : SubRegIndex<32>;
31 def qhisub : SubRegIndex<64>;
32 def qsub : SubRegIndex<64>;
33 def sube64 : SubRegIndex<64>;
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/external/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp286 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction() local
287 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
288 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
301 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction() local
302 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td22 def sub_32 : SubRegIndex<32>;
24 def bsub : SubRegIndex<8>;
25 def hsub : SubRegIndex<16>;
26 def ssub : SubRegIndex<32>;
27 def dsub : SubRegIndex<32>;
28 def sube32 : SubRegIndex<32>;
29 def subo32 : SubRegIndex<32>;
30 def qhisub : SubRegIndex<64>;
31 def qsub : SubRegIndex<64>;
32 def sube64 : SubRegIndex<64>;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64RegisterInfo.td22 def sub_32 : SubRegIndex<32>;
24 def bsub : SubRegIndex<8>;
25 def hsub : SubRegIndex<16>;
26 def ssub : SubRegIndex<32>;
27 def dsub : SubRegIndex<32>;
28 def sube32 : SubRegIndex<32>;
29 def subo32 : SubRegIndex<32>;
30 def qhisub : SubRegIndex<64>;
31 def qsub : SubRegIndex<64>;
32 def sube64 : SubRegIndex<64>;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCQPXLoadSplat.cpp103 unsigned SubRegIndex = in runOnMachineFunction() local
105 Register SplatSubReg = TRI->getSubReg(SplatReg, SubRegIndex); in runOnMachineFunction()
/external/llvm/lib/Target/PowerPC/
DPPCQPXLoadSplat.cpp108 unsigned SubRegIndex = in runOnMachineFunction() local
110 unsigned SplatSubReg = TRI->getSubReg(SplatReg, SubRegIndex); in runOnMachineFunction()
DPPCRegisterInfo.td14 def sub_lt : SubRegIndex<1>;
15 def sub_gt : SubRegIndex<1, 1>;
16 def sub_eq : SubRegIndex<1, 2>;
17 def sub_un : SubRegIndex<1, 3>;
18 def sub_32 : SubRegIndex<32>;
19 def sub_64 : SubRegIndex<64>;
20 def sub_128 : SubRegIndex<128>;
/external/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td24 def subreg_l32 : SubRegIndex<32, 0>; // Also acts as subreg_ll32.
25 def subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_lh32.
26 def subreg_l64 : SubRegIndex<64, 0>;
27 def subreg_h64 : SubRegIndex<64, 64>;
28 def subreg_r32 : SubRegIndex<32, 32>; // Reinterpret a wider reg as 32 bits.
29 def subreg_r64 : SubRegIndex<64, 64>; // Reinterpret a wider reg as 64 bits.
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td13 def sub_lt : SubRegIndex<1>;
14 def sub_gt : SubRegIndex<1, 1>;
15 def sub_eq : SubRegIndex<1, 2>;
16 def sub_un : SubRegIndex<1, 3>;
17 def sub_32 : SubRegIndex<32>;
18 def sub_64 : SubRegIndex<64>;
19 def sub_vsx0 : SubRegIndex<128>;
20 def sub_vsx1 : SubRegIndex<128, 128>;
21 def sub_pair0 : SubRegIndex<256>;
22 def sub_pair1 : SubRegIndex<256, 256>;
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVRegisterInfo.td24 def sub_16 : SubRegIndex<16>;
36 def sub_32 : SubRegIndex<32>;
54 def sub_vrm2 : SubRegIndex<64, -1>;
55 def sub_vrm2_hi : SubRegIndex<64, -1>;
56 def sub_vrm4 : SubRegIndex<128, -1>;
57 def sub_vrm4_hi : SubRegIndex<128, -1>;
58 def sub_vrm8 : SubRegIndex<256, -1>;
59 def sub_vrm8_hi : SubRegIndex<256, -1>;
/external/llvm/lib/Target/ARM/
DARMRegisterInfo.td30 def qqsub_0 : SubRegIndex<256>;
31 def qqsub_1 : SubRegIndex<256, 256>;
34 def qsub_0 : SubRegIndex<128>;
35 def qsub_1 : SubRegIndex<128, 128>;
39 def dsub_0 : SubRegIndex<64>;
40 def dsub_1 : SubRegIndex<64, 64>;
48 def ssub_0 : SubRegIndex<32>;
49 def ssub_1 : SubRegIndex<32, 32>;
53 def gsub_0 : SubRegIndex<32>;
54 def gsub_1 : SubRegIndex<32, 32>;
/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.td14 def sub_32 : SubRegIndex<32>;
15 def sub_64 : SubRegIndex<64>;
16 def sub_lo : SubRegIndex<32>;
17 def sub_hi : SubRegIndex<32, 32>;
18 def sub_dsp16_19 : SubRegIndex<4, 16>;
19 def sub_dsp20 : SubRegIndex<1, 20>;
20 def sub_dsp21 : SubRegIndex<1, 21>;
21 def sub_dsp22 : SubRegIndex<1, 22>;
22 def sub_dsp23 : SubRegIndex<1, 23>;
/external/llvm-project/llvm/lib/Target/CSKY/
DCSKYRegisterInfo.td27 def sub32_0 : SubRegIndex<32, 0>;
28 def sub32_32 : SubRegIndex<32, 32>;
29 def sub64_0 : SubRegIndex<64, 0>;
30 def sub64_64 : SubRegIndex<64,64>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsRegisterInfo.td13 def sub_32 : SubRegIndex<32>;
14 def sub_64 : SubRegIndex<64>;
15 def sub_lo : SubRegIndex<32>;
16 def sub_hi : SubRegIndex<32, 32>;
17 def sub_dsp16_19 : SubRegIndex<4, 16>;
18 def sub_dsp20 : SubRegIndex<1, 20>;
19 def sub_dsp21 : SubRegIndex<1, 21>;
20 def sub_dsp22 : SubRegIndex<1, 22>;
21 def sub_dsp23 : SubRegIndex<1, 23>;
/external/llvm-project/llvm/lib/Target/Mips/
DMipsRegisterInfo.td13 def sub_32 : SubRegIndex<32>;
14 def sub_64 : SubRegIndex<64>;
15 def sub_lo : SubRegIndex<32>;
16 def sub_hi : SubRegIndex<32, 32>;
17 def sub_dsp16_19 : SubRegIndex<4, 16>;
18 def sub_dsp20 : SubRegIndex<1, 20>;
19 def sub_dsp21 : SubRegIndex<1, 21>;
20 def sub_dsp22 : SubRegIndex<1, 22>;
21 def sub_dsp23 : SubRegIndex<1, 23>;

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