Home
last modified time | relevance | path

Searched refs:ULL (Results 1 – 25 of 358) sorted by relevance

12345678910>>...15

/external/capstone/arch/PowerPC/
DPPCGenSubtargetInfo.inc16 #define PPC_DeprecatedDST (1ULL << 0)
17 #define PPC_DeprecatedMFTB (1ULL << 1)
18 #define PPC_Directive32 (1ULL << 2)
19 #define PPC_Directive64 (1ULL << 3)
20 #define PPC_Directive440 (1ULL << 4)
21 #define PPC_Directive601 (1ULL << 5)
22 #define PPC_Directive602 (1ULL << 6)
23 #define PPC_Directive603 (1ULL << 7)
24 #define PPC_Directive604 (1ULL << 8)
25 #define PPC_Directive620 (1ULL << 9)
[all …]
/external/capstone/arch/ARM/
DARMGenSubtargetInfo.inc16 #define ARM_FeatureAClass (1ULL << 0)
17 #define ARM_FeatureAvoidMOVsShOp (1ULL << 1)
18 #define ARM_FeatureAvoidPartialCPSR (1ULL << 2)
19 #define ARM_FeatureCRC (1ULL << 3)
20 #define ARM_FeatureCrypto (1ULL << 4)
21 #define ARM_FeatureD16 (1ULL << 5)
22 #define ARM_FeatureDB (1ULL << 6)
23 #define ARM_FeatureDSPThumb2 (1ULL << 7)
24 #define ARM_FeatureFP16 (1ULL << 8)
25 #define ARM_FeatureFPARMv8 (1ULL << 9)
[all …]
/external/arm-trusted-firmware/include/arch/aarch64/
Darch.h30 #define MPIDR_MT_MASK (ULL(1) << 24)
34 #define MPIDR_AFFLVL_MASK ULL(0xff)
40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
42 #define MPIDR_AFFLVL0 ULL(0x0)
43 #define MPIDR_AFFLVL1 ULL(0x1)
44 #define MPIDR_AFFLVL2 ULL(0x2)
45 #define MPIDR_AFFLVL3 ULL(0x3)
163 #define ID_AA64PFR0_AMU_MASK ULL(0xf)
164 #define ID_AA64PFR0_ELX_MASK ULL(0xf)
167 #define ID_AA64PFR0_GIC_MASK ULL(0xf)
[all …]
/external/arm-trusted-firmware/plat/rpi/rpi3/include/
Drpi_hw.h16 #define RPI_IO_BASE ULL(0x3F000000)
17 #define RPI_IO_SIZE ULL(0x01000000)
22 #define RPI3_MBOX_OFFSET ULL(0x0000B880)
25 #define RPI3_MBOX0_READ_OFFSET ULL(0x00000000)
26 #define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010)
27 #define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014)
28 #define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018)
29 #define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C)
31 #define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020)
32 #define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030)
[all …]
Dplatform_def.h18 #define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
20 #define PLATFORM_STACK_SIZE ULL(0x1000)
67 #define SEC_ROM_BASE ULL(0x00000000)
68 #define SEC_ROM_SIZE ULL(0x00010000)
71 #define PLAT_RPI3_FIP_BASE ULL(0x00020000)
72 #define PLAT_RPI3_FIP_MAX_SIZE ULL(0x00010000)
75 #define SEC_SRAM_BASE ULL(0x00200000)
76 #define SEC_SRAM_SIZE ULL(0x00100000)
78 #define SEC_DRAM0_BASE ULL(0x00300000)
79 #define SEC_DRAM0_SIZE ULL(0x00100000)
[all …]
/external/capstone/arch/Mips/
DMipsGenSubtargetInfo.inc16 #define Mips_FeatureCnMips (1ULL << 0)
17 #define Mips_FeatureDSP (1ULL << 1)
18 #define Mips_FeatureDSPR2 (1ULL << 2)
19 #define Mips_FeatureFP64Bit (1ULL << 3)
20 #define Mips_FeatureFPXX (1ULL << 4)
21 #define Mips_FeatureGP64Bit (1ULL << 5)
22 #define Mips_FeatureMSA (1ULL << 6)
23 #define Mips_FeatureMicroMips (1ULL << 7)
24 #define Mips_FeatureMips1 (1ULL << 8)
25 #define Mips_FeatureMips2 (1ULL << 9)
[all …]
/external/arm-trusted-firmware/plat/rpi/rpi4/include/
Drpi_hw.h16 #define RPI_IO_BASE ULL(0xFE000000)
17 #define RPI_IO_SIZE ULL(0x02000000)
22 #define RPI3_MBOX_OFFSET ULL(0x0000B880)
25 #define RPI3_MBOX0_READ_OFFSET ULL(0x00000000)
26 #define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010)
27 #define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014)
28 #define RPI3_MBOX0_STATUS_OFFSET ULL(0x00000018)
29 #define RPI3_MBOX0_CONFIG_OFFSET ULL(0x0000001C)
31 #define RPI3_MBOX1_WRITE_OFFSET ULL(0x00000020)
32 #define RPI3_MBOX1_PEEK_OFFSET ULL(0x00000030)
[all …]
Dplatform_def.h18 #define RPI3_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
20 #define PLATFORM_STACK_SIZE ULL(0x1000)
82 #define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8)
87 #define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8)
94 #define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0)
95 #define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1)
96 #define PLAT_RPI3_TM_HOLD_STATE_BSP_OFF ULL(2)
104 #define PLAT_MAX_BL31_SIZE ULL(0x80000)
106 #define BL31_BASE ULL(0x1000)
107 #define BL31_LIMIT ULL(0x80000)
[all …]
/external/capstone/arch/SystemZ/
DSystemZGenSubtargetInfo.inc17 SystemZ_FeatureDFPPackedConversion = 1ULL << 0,
18 SystemZ_FeatureDFPZonedConversion = 1ULL << 1,
19 SystemZ_FeatureDistinctOps = 1ULL << 2,
20 SystemZ_FeatureEnhancedDAT2 = 1ULL << 3,
21 SystemZ_FeatureExecutionHint = 1ULL << 4,
22 SystemZ_FeatureFPExtension = 1ULL << 5,
23 SystemZ_FeatureFastSerialization = 1ULL << 6,
24 SystemZ_FeatureGuardedStorage = 1ULL << 7,
25 SystemZ_FeatureHighWord = 1ULL << 8,
26 SystemZ_FeatureInsertReferenceBitsMultiple = 1ULL << 9,
[all …]
/external/protobuf/objectivec/Tests/
DGPBDictionaryTests+UInt64.m43 //%PDDM-EXPAND TEST_FOR_POD_KEY(UInt64, uint64_t, 31ULL, 32ULL, 33ULL, 34ULL)
88 XCTAssertFalse([dict getUInt32:NULL forKey:31ULL]);
98 [dict setUInt32:100U forKey:31ULL];
102 XCTAssertTrue([dict getUInt32:NULL forKey:31ULL]);
103 XCTAssertTrue([dict getUInt32:&value forKey:31ULL]);
105 XCTAssertFalse([dict getUInt32:NULL forKey:32ULL]);
107 XCTAssertEqual(aKey, 31ULL);
115 const uint64_t kKeys[] = { 31ULL, 32ULL, 33ULL };
124 XCTAssertTrue([dict getUInt32:NULL forKey:31ULL]);
125 XCTAssertTrue([dict getUInt32:&value forKey:31ULL]);
[all …]
/external/arm-trusted-firmware/include/lib/cpus/aarch64/
Dcortex_a57.h30 #define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
31 #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
32 #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
33 #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
36 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
48 #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59)
49 #define CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION (ULL(1) << 58)
50 #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55)
51 #define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
52 #define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52)
[all …]
Dcortex_a72.h20 #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
21 #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
22 #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
23 #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
35 #define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
36 #define CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55)
37 #define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
38 #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
39 #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
46 #define CORTEX_A72_L2ACTLR_FORCE_TAG_BANK_CLK_ACTIVE (ULL(1) << 28)
[all …]
Dneoverse_n1.h36 #define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24)
37 #define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51)
38 #define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
45 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6)
46 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
50 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
51 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
52 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11)
53 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15)
54 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16)
[all …]
Drainier.h36 #define RAINIER_WS_THR_L2_MASK (ULL(3) << 24)
37 #define RAINIER_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51)
44 #define RAINIER_CPUACTLR_EL1_BIT_6 (ULL(1) << 6)
45 #define RAINIER_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
49 #define RAINIER_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)
50 #define RAINIER_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
51 #define RAINIER_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11)
52 #define RAINIER_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15)
53 #define RAINIER_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16)
54 #define RAINIER_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)
[all …]
/external/arm-trusted-firmware/include/lib/cpus/aarch32/
Dcortex_a57.h29 #define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
30 #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
31 #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
32 #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
35 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
47 #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)
48 #define CORTEX_A57_CPUACTLR_DIS_DMB_NULLIFICATION (ULL(1) << 58)
49 #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55)
50 #define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
51 #define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52)
[all …]
Dcortex_a72.h20 #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
21 #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
22 #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
23 #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
35 #define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
36 #define CORTEX_A72_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55)
37 #define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
38 #define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
39 #define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32)
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenInstrInfo.inc5846 …{ 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandI…
5847 …{ 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr,…
5848 …{ 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<M…
5849 …{ 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
5850 …{ 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
5851 …{ 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
5852 …{ 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
5853 …{ 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr,…
5854 …{ 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, /…
5855 …{ 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, /…
[all …]
/external/strace/xlat/
Dbtrfs_tree_objectids.in2 BTRFS_ROOT_TREE_OBJECTID 1ULL
3 BTRFS_EXTENT_TREE_OBJECTID 2ULL
4 BTRFS_CHUNK_TREE_OBJECTID 3ULL
5 BTRFS_DEV_TREE_OBJECTID 4ULL
6 BTRFS_FS_TREE_OBJECTID 5ULL
7 BTRFS_ROOT_TREE_DIR_OBJECTID 6ULL
8 BTRFS_CSUM_TREE_OBJECTID 7ULL
9 BTRFS_QUOTA_TREE_OBJECTID 8ULL
10 BTRFS_UUID_TREE_OBJECTID 9ULL
11 BTRFS_FREE_SPACE_TREE_OBJECTID 10ULL
[all …]
Dbtrfs_balance_args.in2 BTRFS_BALANCE_ARGS_PROFILES (1ULL << 0)
3 BTRFS_BALANCE_ARGS_USAGE (1ULL << 1)
4 BTRFS_BALANCE_ARGS_DEVID (1ULL << 2)
5 BTRFS_BALANCE_ARGS_DRANGE (1ULL << 3)
6 BTRFS_BALANCE_ARGS_VRANGE (1ULL << 4)
7 BTRFS_BALANCE_ARGS_LIMIT (1ULL << 5)
8 BTRFS_BALANCE_ARGS_LIMIT_RANGE (1ULL << 6)
9 BTRFS_BALANCE_ARGS_STRIPES_RANGE (1ULL << 7)
10 BTRFS_BALANCE_ARGS_CONVERT (1ULL << 8)
11 BTRFS_BALANCE_ARGS_SOFT (1ULL << 9)
[all …]
Dbtrfs_space_info_flags.in2 BTRFS_BLOCK_GROUP_DATA (1ULL << 0)
3 BTRFS_BLOCK_GROUP_SYSTEM (1ULL << 1)
4 BTRFS_BLOCK_GROUP_METADATA (1ULL << 2)
5 BTRFS_BLOCK_GROUP_RAID0 (1ULL << 3)
6 BTRFS_BLOCK_GROUP_RAID1 (1ULL << 4)
7 BTRFS_BLOCK_GROUP_DUP (1ULL << 5)
8 BTRFS_BLOCK_GROUP_RAID10 (1ULL << 6)
9 BTRFS_BLOCK_GROUP_RAID5 (1ULL << 7)
10 BTRFS_BLOCK_GROUP_RAID6 (1ULL << 8)
11 BTRFS_AVAIL_ALLOC_BIT_SINGLE (1ULL << 48)
[all …]
Dbtrfs_features_incompat.in2 BTRFS_FEATURE_INCOMPAT_MIXED_BACKREF (1ULL << 0)
3 BTRFS_FEATURE_INCOMPAT_DEFAULT_SUBVOL (1ULL << 1)
4 BTRFS_FEATURE_INCOMPAT_MIXED_GROUPS (1ULL << 2)
5 BTRFS_FEATURE_INCOMPAT_COMPRESS_LZO (1ULL << 3)
6 BTRFS_FEATURE_INCOMPAT_COMPRESS_LZOv2 (1ULL << 4)
7 BTRFS_FEATURE_INCOMPAT_BIG_METADATA (1ULL << 5)
8 BTRFS_FEATURE_INCOMPAT_EXTENDED_IREF (1ULL << 6)
9 BTRFS_FEATURE_INCOMPAT_RAID56 (1ULL << 7)
10 BTRFS_FEATURE_INCOMPAT_SKINNY_METADATA (1ULL << 8)
11 BTRFS_FEATURE_INCOMPAT_NO_HOLES (1ULL << 9)
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenInstrInfo.inc4861 …{ 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandI…
4862 …{ 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr,…
4863 …{ 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<M…
4864 …{ 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
4865 …{ 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
4866 …{ 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
4867 …{ 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
4868 …{ 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr,…
4869 …{ 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, /…
4870 …{ 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, /…
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenInstrInfo.inc2984 …{ 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandI…
2985 …{ 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr,…
2986 …{ 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<M…
2987 …{ 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
2988 …{ 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
2989 …{ 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
2990 …{ 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
2991 …{ 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr,…
2992 …{ 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, /…
2993 …{ 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, /…
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenInstrInfo.inc17700 …{ 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandI…
17701 …{ 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr,…
17702 …{ 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<M…
17703 …{ 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
17704 …{ 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
17705 …{ 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
17706 …{ 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
17707 …{ 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr,…
17708 …{ 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, /…
17709 …{ 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, /…
[all …]
/external/arm-trusted-firmware/include/lib/xlat_tables/
Dxlat_tables_defs.h52 #define XN (ULL(1) << 2)
54 #define UXN (ULL(1) << 2)
55 #define PXN (ULL(1) << 1)
56 #define CONT_HINT (ULL(1) << 0)
57 #define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52)
67 #define GP (ULL(1) << 50)
70 #define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000)
116 (((virtual_addr) >> XLAT_ADDR_SHIFT(level)) & ULL(0x1FF))
127 #define AP2_RO ULL(0x1)
128 #define AP2_RW ULL(0x0)
[all …]

12345678910>>...15