Searched refs:UMAX (Results 1 – 25 of 114) sorted by relevance
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15 ; SI: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[COPY]], [[COPY1]]16 ; SI: $vgpr0 = COPY [[UMAX]](s32)20 ; VI: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[COPY]], [[COPY1]]21 ; VI: $vgpr0 = COPY [[UMAX]](s32)25 ; GFX9: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[COPY]], [[COPY1]]26 ; GFX9: $vgpr0 = COPY [[UMAX]](s32)77 ; SI: [[UMAX:%[0-9]+]]:_(s32) = G_UMAX [[AND]], [[AND1]]78 ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UMAX]](s32)85 ; VI: [[UMAX:%[0-9]+]]:_(s16) = G_UMAX [[TRUNC]], [[TRUNC1]]86 ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMAX]](s16)[all …]
37 ; CHECK: [[UMAX:%[0-9]+]]:vgpr(s32) = G_UMAX [[COPY2]], [[COPY1]]38 ; CHECK: $vgpr0 = COPY [[UMAX]](s32)57 ; CHECK: [[UMAX:%[0-9]+]]:vgpr(s32) = G_UMAX [[COPY]], [[COPY2]]58 ; CHECK: $vgpr0 = COPY [[UMAX]](s32)76 ; CHECK: [[UMAX:%[0-9]+]]:vgpr(s32) = G_UMAX [[COPY]], [[COPY1]]77 ; CHECK: $vgpr0 = COPY [[UMAX]](s32)210 ; CHECK: [[UMAX:%[0-9]+]]:vgpr(<2 x s16>) = G_UMAX [[COPY2]], [[COPY1]]211 ; CHECK: $vgpr0 = COPY [[UMAX]](<2 x s16>)230 ; CHECK: [[UMAX:%[0-9]+]]:vgpr(<2 x s16>) = G_UMAX [[COPY]], [[COPY2]]231 ; CHECK: $vgpr0 = COPY [[UMAX]](<2 x s16>)[all …]
204 ; CHECK-V8-NEXT: [[UMAX:%.*]] = select i1 [[UGT]], i32 [[DATA_A]], i32 [[DATA_B]]205 ; CHECK-V8-NEXT: [[ACC_NEXT:%.*]] = add i32 [[UMAX]], [[ACC]]207 ; CHECK-V8-NEXT: store i32 [[UMAX]], i32* [[ADDR_C]], align 4260 ; CHECK-V8-NEXT: [[UMAX:%.*]] = select i1 [[UGT]], i32 [[DATA_A]], i32 [[DATA_B]]261 ; CHECK-V8-NEXT: [[ACC_NEXT:%.*]] = add i32 [[UMAX]], [[ACC]]263 ; CHECK-V8-NEXT: store i32 [[UMAX]], i32* [[ADDR_C]], align 4316 ; CHECK-V8-NEXT: [[UMAX:%.*]] = select i1 [[UGT]], i64 [[DATA_A]], i64 [[DATA_B]]317 ; CHECK-V8-NEXT: [[ACC_NEXT]] = add i64 [[UMAX]], [[ACC]]319 ; CHECK-V8-NEXT: store i64 [[UMAX]], i64* [[ADDR_C]], align 4362 ; CHECK-V8-NEXT: [[UMAX:%.*]] = select i1 [[UGT]], i64 [[DATA_A]], i64 [[DATA_B]][all …]
139 ; CHECK-V8M-NEXT: [[UMAX:%.*]] = select i1 [[TMP0]], i32 [[N]], i32 1140 ; CHECK-V8M-NEXT: [[TMP1:%.*]] = add i32 [[UMAX]], -1167 ; CHECK-V8A-NEXT: [[UMAX:%.*]] = select i1 [[TMP0]], i32 [[N]], i32 1168 ; CHECK-V8A-NEXT: [[TMP1:%.*]] = add i32 [[UMAX]], -1309 ; CHECK-V8M-NEXT: [[UMAX:%.*]] = select i1 [[TMP2]], i32 [[N]], i32 1310 ; CHECK-V8M-NEXT: [[TMP3:%.*]] = add i32 [[UMAX]], -1344 ; CHECK-V8A-NEXT: [[UMAX:%.*]] = select i1 [[TMP2]], i32 [[N]], i32 1345 ; CHECK-V8A-NEXT: [[TMP3:%.*]] = add i32 [[UMAX]], -1416 ; CHECK-V8M-NEXT: [[UMAX:%.*]] = select i1 [[TMP4]], i32 [[N]], i32 1417 ; CHECK-V8M-NEXT: [[TMP5:%.*]] = add i32 [[UMAX]], -1[all …]
8 { OR1K_ATOMIC_UMAX, "UMAX" },
107 UMAX = 2*(sys.maxint+1)114 val -= UMAX
18 ; CHECK-NEXT: [[UMAX:%.*]] = select i1 [[TMP3]], i64 [[TMP2]], i64 119 ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX]], 1633 ; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[UMAX]], -1665 ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX]], [[N_VEC]]
12 ; CHECK-NEXT: [[UMAX:%.*]] = select i1 [[TMP0]], i32 [[N]], i32 113 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[UMAX]], -195 ; CHECK-NEXT: [[UMAX:%.*]] = select i1 [[TMP0]], i32 [[LENGTH]], i32 196 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[UMAX]], -1179 ; CHECK-NEXT: [[UMAX:%.*]] = select i1 [[TMP1]], i32 [[N]], i32 1180 ; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[UMAX]], -1356 ; CHECK-NEXT: [[UMAX:%.*]] = select i1 [[TMP0]], i32 [[N]], i32 1357 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[UMAX]], -1685 ; CHECK-NEXT: [[UMAX:%.*]] = select i1 [[TMP0]], i32 [[N]], i32 1686 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[UMAX]], -1[all …]
11 ; CHECK-NEXT: [[UMAX:%.*]] = select i1 [[TMP0]], i32 [[N]], i32 112 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[UMAX]], -1239 ; CHECK-NEXT: [[UMAX:%.*]] = select i1 [[TMP2]], i32 [[N]], i32 1240 ; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[UMAX]], -1311 ; CHECK-NEXT: [[UMAX:%.*]] = select i1 [[TMP4]], i32 [[N]], i32 1312 ; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[UMAX]], -1386 ; CHECK-NEXT: [[UMAX:%.*]] = select i1 [[TMP1]], i32 [[N]], i32 1387 ; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[UMAX]], -1462 ; CHECK-NEXT: [[UMAX:%.*]] = select i1 [[TMP0]], i32 [[N]], i32 1463 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[UMAX]], -1[all …]
192 ; (X <u C1) ? C1 : UMIN(X, C2) ==> UMAX(UMIN(X, C2), C1)207 ; (X >u C1) ? C1 : UMAX(X, C2) ==> UMIN(UMAX(X, C2), C1)
161 OP12(UMAX)
325 SMIN, SMAX, UMIN, UMAX, enumerator
152 OP12(UMAX)
133 OPCODE(1, 2, COMP, UMAX)
960 X86_INTRINSIC_DATA(avx512_mask_pmaxu_b_128, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),961 X86_INTRINSIC_DATA(avx512_mask_pmaxu_b_256, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),962 X86_INTRINSIC_DATA(avx512_mask_pmaxu_b_512, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),963 X86_INTRINSIC_DATA(avx512_mask_pmaxu_d_128, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),964 X86_INTRINSIC_DATA(avx512_mask_pmaxu_d_256, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),965 X86_INTRINSIC_DATA(avx512_mask_pmaxu_d_512, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),966 X86_INTRINSIC_DATA(avx512_mask_pmaxu_q_128, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),967 X86_INTRINSIC_DATA(avx512_mask_pmaxu_q_256, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),968 X86_INTRINSIC_DATA(avx512_mask_pmaxu_q_512, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),969 X86_INTRINSIC_DATA(avx512_mask_pmaxu_w_128, INTR_TYPE_2OP_MASK, ISD::UMAX, 0),[all …]
445 SMIN, SMAX, UMIN, UMAX, enumerator
2337 { ISD::UMAX, MVT::v32i16, 1 }, in getTypeBasedIntrinsicInstrCost()2338 { ISD::UMAX, MVT::v64i8, 1 }, in getTypeBasedIntrinsicInstrCost()2379 { ISD::UMAX, MVT::v8i64, 1 }, in getTypeBasedIntrinsicInstrCost()2380 { ISD::UMAX, MVT::v16i32, 1 }, in getTypeBasedIntrinsicInstrCost()2381 { ISD::UMAX, MVT::v32i16, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()2382 { ISD::UMAX, MVT::v64i8, 2 }, // FIXME: include split in getTypeBasedIntrinsicInstrCost()2383 { ISD::UMAX, MVT::v4i64, 1 }, in getTypeBasedIntrinsicInstrCost()2384 { ISD::UMAX, MVT::v2i64, 1 }, in getTypeBasedIntrinsicInstrCost()2467 { ISD::UMAX, MVT::v8i32, 1 }, in getTypeBasedIntrinsicInstrCost()2468 { ISD::UMAX, MVT::v16i16, 1 }, in getTypeBasedIntrinsicInstrCost()[all …]
578 UMAX, enumerator
126 ; CHECK-NEXT: [[UMAX:%.*]] = select i1 [[TMP0]], i32 [[LIM]], i32 2127 ; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[UMAX]] to i64
256 ; CHECK-NEXT: [[UMAX:%.*]] = select i1 [[TMP0]], i32 [[N]], i32 -2257 ; CHECK-NEXT: [[TMP1:%.*]] = add nsw i32 [[UMAX]], 1334 ; CHECK-NEXT: [[UMAX:%.*]] = select i1 [[TMP0]], i32 [[N]], i32 1335 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[UMAX]], 1
93 def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
86 ; No i64 vector support for UMAX.
434 ; (X <u C1) ? C1 : UMIN(X, C2) ==> UMAX(UMIN(X, C2), C1)451 ; (X >u C1) ? C1 : UMAX(X, C2) ==> UMIN(UMAX(X, C2), C1)468 ; (X >u C1) ? UMIN(X, C2) : C1 ==> UMAX(UMIN(X, C2), C1)485 ; (X <u C1) ? UMAX(X, C2) : C1 ==> UMIN(UMAX(X, C2), C1)
783 ; CHECK-NEXT: [[UMAX:%.*]] = select i1 [[CMP1]], i32 [[NOTX]], i32 [[Y]]784 ; CHECK-NEXT: [[UMIN:%.*]] = xor i32 [[UMAX]], -1785 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[UMAX]], [[Z:%.*]]
210 case ISD::UMAX: return "umax"; in getOperationName()