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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dloop-prefetch.ll1 ; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs -asm-verbose=0 < %s | FileCheck --chec…
2 ; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s -filetype=obj | llvm-objdump -d -…
3 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=GFX8 %s
27 tail call void @llvm.amdgcn.s.sleep(i32 0)
52 tail call void @llvm.amdgcn.s.sleep(i32 0)
53 tail call void @llvm.amdgcn.s.sleep(i32 0)
54 tail call void @llvm.amdgcn.s.sleep(i32 0)
55 tail call void @llvm.amdgcn.s.sleep(i32 0)
56 tail call void @llvm.amdgcn.s.sleep(i32 0)
57 tail call void @llvm.amdgcn.s.sleep(i32 0)
[all …]
Ddirective-amdgcn-target.ll1 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 < %s | FileCheck --check-prefixes=GFX600 %s
2 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti < %s | FileCheck --check-prefixes=GFX600 %s
3 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx601 < %s | FileCheck --check-prefixes=GFX601 %s
4 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=pitcairn < %s | FileCheck --check-prefixes=GFX601 %s
5 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=verde < %s | FileCheck --check-prefixes=GFX601 %s
6 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx602 < %s | FileCheck --check-prefixes=GFX602 %s
7 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hainan < %s | FileCheck --check-prefixes=GFX602 %s
8 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=oland < %s | FileCheck --check-prefixes=GFX602 %s
9 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck --check-prefixes=GFX700 %s
10 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck --check-prefixes=GFX700 %s
[all …]
Dllvm.amdgcn.s.incperflevel.ll1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
4 declare void @llvm.amdgcn.s.incperflevel(i32) #0
24 call void @llvm.amdgcn.s.incperflevel(i32 0)
25 call void @llvm.amdgcn.s.incperflevel(i32 1)
26 call void @llvm.amdgcn.s.incperflevel(i32 2)
27 call void @llvm.amdgcn.s.incperflevel(i32 3)
28 call void @llvm.amdgcn.s.incperflevel(i32 4)
29 call void @llvm.amdgcn.s.incperflevel(i32 5)
30 call void @llvm.amdgcn.s.incperflevel(i32 6)
[all …]
Dllvm.amdgcn.s.sleep.ll1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
4 declare void @llvm.amdgcn.s.sleep(i32) #0
24 call void @llvm.amdgcn.s.sleep(i32 0)
25 call void @llvm.amdgcn.s.sleep(i32 1)
26 call void @llvm.amdgcn.s.sleep(i32 2)
27 call void @llvm.amdgcn.s.sleep(i32 3)
28 call void @llvm.amdgcn.s.sleep(i32 4)
29 call void @llvm.amdgcn.s.sleep(i32 5)
30 call void @llvm.amdgcn.s.sleep(i32 6)
[all …]
Dllvm.amdgcn.s.decperflevel.ll1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
4 declare void @llvm.amdgcn.s.decperflevel(i32) #0
24 call void @llvm.amdgcn.s.decperflevel(i32 0)
25 call void @llvm.amdgcn.s.decperflevel(i32 1)
26 call void @llvm.amdgcn.s.decperflevel(i32 2)
27 call void @llvm.amdgcn.s.decperflevel(i32 3)
28 call void @llvm.amdgcn.s.decperflevel(i32 4)
29 call void @llvm.amdgcn.s.decperflevel(i32 5)
30 call void @llvm.amdgcn.s.decperflevel(i32 6)
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.s.sleep.ll1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
4 declare void @llvm.amdgcn.s.sleep(i32) #0
24 call void @llvm.amdgcn.s.sleep(i32 0)
25 call void @llvm.amdgcn.s.sleep(i32 1)
26 call void @llvm.amdgcn.s.sleep(i32 2)
27 call void @llvm.amdgcn.s.sleep(i32 3)
28 call void @llvm.amdgcn.s.sleep(i32 4)
29 call void @llvm.amdgcn.s.sleep(i32 5)
30 call void @llvm.amdgcn.s.sleep(i32 6)
[all …]
/external/llvm-project/llvm/test/Transforms/InstSimplify/ConstProp/AMDGPU/
Dcos.ll4 declare half @llvm.amdgcn.cos.f16(half) #0
5 declare float @llvm.amdgcn.cos.f32(float) #0
6 declare double @llvm.amdgcn.cos.f64(double) #0
22 ; CHECK-NEXT: [[P1000:%.*]] = call half @llvm.amdgcn.cos.f16(half 0xH63D0)
24 ; CHECK-NEXT: [[N1000:%.*]] = call half @llvm.amdgcn.cos.f16(half 0xHE3D0)
26 ; CHECK-NEXT: [[PINF:%.*]] = call half @llvm.amdgcn.cos.f16(half 0xH7C00)
28 ; CHECK-NEXT: [[NINF:%.*]] = call half @llvm.amdgcn.cos.f16(half 0xHFC00)
30 ; CHECK-NEXT: [[NAN:%.*]] = call half @llvm.amdgcn.cos.f16(half 0xH7E00)
34 %p0 = call half @llvm.amdgcn.cos.f16(half +0.0)
36 %n0 = call half @llvm.amdgcn.cos.f16(half -0.0)
[all …]
Dsin.ll4 declare half @llvm.amdgcn.sin.f16(half) #0
5 declare float @llvm.amdgcn.sin.f32(float) #0
6 declare double @llvm.amdgcn.sin.f64(double) #0
22 ; CHECK-NEXT: [[P1000:%.*]] = call half @llvm.amdgcn.sin.f16(half 0xH63D0)
24 ; CHECK-NEXT: [[N1000:%.*]] = call half @llvm.amdgcn.sin.f16(half 0xHE3D0)
26 ; CHECK-NEXT: [[PINF:%.*]] = call half @llvm.amdgcn.sin.f16(half 0xH7C00)
28 ; CHECK-NEXT: [[NINF:%.*]] = call half @llvm.amdgcn.sin.f16(half 0xHFC00)
30 ; CHECK-NEXT: [[NAN:%.*]] = call half @llvm.amdgcn.sin.f16(half 0xH7E00)
34 %p0 = call half @llvm.amdgcn.sin.f16(half +0.0)
36 %n0 = call half @llvm.amdgcn.sin.f16(half -0.0)
[all …]
Dcubetc.ll4 declare float @llvm.amdgcn.cubetc(float, float, float)
58 %p3p4p5 = call float @llvm.amdgcn.cubetc(float +3.0, float +4.0, float +5.0)
60 %p3p5p4 = call float @llvm.amdgcn.cubetc(float +3.0, float +5.0, float +4.0)
62 %p4p3p5 = call float @llvm.amdgcn.cubetc(float +4.0, float +3.0, float +5.0)
64 %p4p5p3 = call float @llvm.amdgcn.cubetc(float +4.0, float +5.0, float +3.0)
66 %p5p3p4 = call float @llvm.amdgcn.cubetc(float +5.0, float +3.0, float +4.0)
68 %p5p4p3 = call float @llvm.amdgcn.cubetc(float +5.0, float +4.0, float +3.0)
70 %p3p4n5 = call float @llvm.amdgcn.cubetc(float +3.0, float +4.0, float -5.0)
72 %p3p5n4 = call float @llvm.amdgcn.cubetc(float +3.0, float +5.0, float -4.0)
74 %p4p3n5 = call float @llvm.amdgcn.cubetc(float +4.0, float +3.0, float -5.0)
[all …]
Dcubesc.ll4 declare float @llvm.amdgcn.cubesc(float, float, float)
58 %p3p4p5 = call float @llvm.amdgcn.cubesc(float +3.0, float +4.0, float +5.0)
60 %p3p5p4 = call float @llvm.amdgcn.cubesc(float +3.0, float +5.0, float +4.0)
62 %p4p3p5 = call float @llvm.amdgcn.cubesc(float +4.0, float +3.0, float +5.0)
64 %p4p5p3 = call float @llvm.amdgcn.cubesc(float +4.0, float +5.0, float +3.0)
66 %p5p3p4 = call float @llvm.amdgcn.cubesc(float +5.0, float +3.0, float +4.0)
68 %p5p4p3 = call float @llvm.amdgcn.cubesc(float +5.0, float +4.0, float +3.0)
70 %p3p4n5 = call float @llvm.amdgcn.cubesc(float +3.0, float +4.0, float -5.0)
72 %p3p5n4 = call float @llvm.amdgcn.cubesc(float +3.0, float +5.0, float -4.0)
74 %p4p3n5 = call float @llvm.amdgcn.cubesc(float +4.0, float +3.0, float -5.0)
[all …]
Dcubema.ll4 declare float @llvm.amdgcn.cubema(float, float, float)
58 %p3p4p5 = call float @llvm.amdgcn.cubema(float +3.0, float +4.0, float +5.0)
60 %p3p5p4 = call float @llvm.amdgcn.cubema(float +3.0, float +5.0, float +4.0)
62 %p4p3p5 = call float @llvm.amdgcn.cubema(float +4.0, float +3.0, float +5.0)
64 %p4p5p3 = call float @llvm.amdgcn.cubema(float +4.0, float +5.0, float +3.0)
66 %p5p3p4 = call float @llvm.amdgcn.cubema(float +5.0, float +3.0, float +4.0)
68 %p5p4p3 = call float @llvm.amdgcn.cubema(float +5.0, float +4.0, float +3.0)
70 %p3p4n5 = call float @llvm.amdgcn.cubema(float +3.0, float +4.0, float -5.0)
72 %p3p5n4 = call float @llvm.amdgcn.cubema(float +3.0, float +5.0, float -4.0)
74 %p4p3n5 = call float @llvm.amdgcn.cubema(float +4.0, float +3.0, float -5.0)
[all …]
Dcubeid.ll4 declare float @llvm.amdgcn.cubeid(float, float, float)
58 %p3p4p5 = call float @llvm.amdgcn.cubeid(float +3.0, float +4.0, float +5.0)
60 %p3p5p4 = call float @llvm.amdgcn.cubeid(float +3.0, float +5.0, float +4.0)
62 %p4p3p5 = call float @llvm.amdgcn.cubeid(float +4.0, float +3.0, float +5.0)
64 %p4p5p3 = call float @llvm.amdgcn.cubeid(float +4.0, float +5.0, float +3.0)
66 %p5p3p4 = call float @llvm.amdgcn.cubeid(float +5.0, float +3.0, float +4.0)
68 %p5p4p3 = call float @llvm.amdgcn.cubeid(float +5.0, float +4.0, float +3.0)
70 %p3p4n5 = call float @llvm.amdgcn.cubeid(float +3.0, float +4.0, float -5.0)
72 %p3p5n4 = call float @llvm.amdgcn.cubeid(float +3.0, float +5.0, float -4.0)
74 %p4p3n5 = call float @llvm.amdgcn.cubeid(float +4.0, float +3.0, float -5.0)
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dllvm.amdgcn.s.sleep.ll1 ; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2 ; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-pre…
4 declare void @llvm.amdgcn.s.sleep(i32) #0
24 call void @llvm.amdgcn.s.sleep(i32 0)
25 call void @llvm.amdgcn.s.sleep(i32 1)
26 call void @llvm.amdgcn.s.sleep(i32 2)
27 call void @llvm.amdgcn.s.sleep(i32 3)
28 call void @llvm.amdgcn.s.sleep(i32 4)
29 call void @llvm.amdgcn.s.sleep(i32 5)
30 call void @llvm.amdgcn.s.sleep(i32 6)
[all …]
Dllvm.amdgcn.ds.gws.barrier.ll1 …amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.barrier.ll |…
2 …amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.barrier.ll |…
3 …amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.barrier.ll | F…
4 …amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.barrier.ll |…
5 …amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.…
8 …amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=postrapseudos -o - -verify-machineinstrs < %S/../llvm.…
9 …amdgcn-mesa-mesa3d -mcpu=gfx900 -stop-after=postrapseudos -o - -verify-machineinstrs < %S/../llvm.…
Dllvm.amdgcn.ds.gws.init.ll1 …amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.init.ll | Fi…
2 …amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.init.ll | Fi…
3 …amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.init.ll | File…
4 …amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.init.ll | Fi…
5 …amdgcn-mesa-mesa3d -mcpu=gfx1010 -asm-verbose=0 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.…
Dllvm.amdgcn.ds.gws.sema.br.ll1 …amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.br.ll |…
2 …amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.br.ll |…
3 …amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.br.ll | F…
4 …amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.br.ll |…
5 …amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.br.ll …
Dllvm.amdgcn.ds.gws.sema.v.ll1 …amdgcn-mesa-mesa3d -mcpu=tahiti -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.v.ll | …
2 …amdgcn-mesa-mesa3d -mcpu=hawaii -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.v.ll | …
3 …amdgcn-mesa-mesa3d -mcpu=fiji -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.v.ll | Fi…
4 …amdgcn-mesa-mesa3d -mcpu=gfx900 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.v.ll | …
5 …amdgcn-mesa-mesa3d -mcpu=gfx1010 -o - -verify-machineinstrs < %S/../llvm.amdgcn.ds.gws.sema.v.ll |…
/external/llvm-project/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/
Dllvm.amdgcn.buffer.atomic.ll1 ;RUN: opt -mtriple=amdgcn-mesa-mesa3d -analyze -divergence -use-gpu-divergence-analysis %s | FileCh…
3 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(
6 …%orig = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 …
11 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.add.i32(
14 …%orig = call i32 @llvm.amdgcn.buffer.atomic.add.i32(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
19 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.sub.i32(
22 …%orig = call i32 @llvm.amdgcn.buffer.atomic.sub.i32(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
27 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.smin.i32(
30 …%orig = call i32 @llvm.amdgcn.buffer.atomic.smin.i32(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 …
35 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.umin.i32(
[all …]
/external/llvm-project/clang/test/Driver/
Drocm-device-libs.cl7 // RUN: %clang -### -target amdgcn-amd-amdhsa \
16 // RUN: %clang -### -target amdgcn-amd-amdhsa \
25 // RUN: %clang -### -target amdgcn-amd-amdhsa \
33 // RUN: %clang -### -target amdgcn-amd-amdhsa \
41 // RUN: %clang -### -target amdgcn-amd-amdhsa \
50 // RUN: %clang -### -target amdgcn-amd-amdhsa \
59 // RUN: %clang -### -target amdgcn-amd-amdhsa \
68 // RUN: %clang -### -target amdgcn-amd-amdhsa \
77 // RUN: %clang -### -target amdgcn-amd-amdhsa \
84 // RUN: %clang -### -target amdgcn-amd-amdhsa \
[all …]
Damdgpu-mcpu.cl55 // RUN: %clang -### -target amdgcn %s 2>&1 | FileCheck --check-prefix=GCNDEFAULT %s
56 // RUN: %clang -### -target amdgcn -mcpu=gfx600 %s 2>&1 | FileCheck --check-prefix=GFX600 %s
57 // RUN: %clang -### -target amdgcn -mcpu=tahiti %s 2>&1 | FileCheck --check-prefix=GFX600 %s
58 // RUN: %clang -### -target amdgcn -mcpu=gfx601 %s 2>&1 | FileCheck --check-prefix=GFX601 %s
59 // RUN: %clang -### -target amdgcn -mcpu=pitcairn %s 2>&1 | FileCheck --check-prefix=GFX601 %s
60 // RUN: %clang -### -target amdgcn -mcpu=verde %s 2>&1 | FileCheck --check-prefix=GFX601 %s
61 // RUN: %clang -### -target amdgcn -mcpu=gfx602 %s 2>&1 | FileCheck --check-prefix=GFX602 %s
62 // RUN: %clang -### -target amdgcn -mcpu=hainan %s 2>&1 | FileCheck --check-prefix=GFX602 %s
63 // RUN: %clang -### -target amdgcn -mcpu=oland %s 2>&1 | FileCheck --check-prefix=GFX602 %s
64 // RUN: %clang -### -target amdgcn -mcpu=gfx700 %s 2>&1 | FileCheck --check-prefix=GFX700 %s
[all …]
/external/llvm/test/Transforms/InstCombine/
Damdgcn-intrinsics.ll4 ; llvm.amdgcn.rcp
7 declare float @llvm.amdgcn.rcp.f32(float) nounwind readnone
8 declare double @llvm.amdgcn.rcp.f64(double) nounwind readnone
14 %val = call float @llvm.amdgcn.rcp.f32(float 1.0) nounwind readnone
21 %val = call double @llvm.amdgcn.rcp.f64(double 1.0) nounwind readnone
28 %val = call float @llvm.amdgcn.rcp.f32(float 0.5) nounwind readnone
35 %val = call double @llvm.amdgcn.rcp.f64(double 0.5) nounwind readnone
40 ; CHECK-NEXT: call float @llvm.amdgcn.rcp.f32(float 4.300000e+01)
42 %val = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) nounwind readnone
47 ; CHECK-NEXT: call double @llvm.amdgcn.rcp.f64(double 4.300000e+01)
[all …]
/external/llvm-project/llvm/test/Verifier/AMDGPU/
Dintrinsic-immarg.ll3 declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1)
7 …; CHECK-NEXT: %data0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs…
8 …%data0 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 %bool, i1…
12 …; CHECK-NEXT: %data1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs…
13 …%data1 = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1…
17 declare float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32>, i32, i32, i32)
21 …; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 %…
22 …%data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 %arg)
26 declare float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32>, i32, i32, i32)
30 …; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 %ofs…
[all …]
/external/llvm-project/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/
Dllvm.amdgcn.buffer.atomic.ll1 ;RUN: opt -mtriple=amdgcn-mesa-mesa3d -amdgpu-use-legacy-divergence-analysis -analyze -divergence %…
3 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(
6 …%orig = call i32 @llvm.amdgcn.buffer.atomic.swap.i32(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 …
11 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.add.i32(
14 …%orig = call i32 @llvm.amdgcn.buffer.atomic.add.i32(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
19 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.sub.i32(
22 …%orig = call i32 @llvm.amdgcn.buffer.atomic.sub.i32(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
27 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.smin.i32(
30 …%orig = call i32 @llvm.amdgcn.buffer.atomic.smin.i32(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 …
35 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.umin.i32(
[all …]
/external/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/
Dllvm.amdgcn.buffer.atomic.ll1 ;RUN: opt -mtriple=amdgcn-mesa-mesa3d -analyze -divergence %s | FileCheck %s
3 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.swap(
6 %orig = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
11 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.add(
14 %orig = call i32 @llvm.amdgcn.buffer.atomic.add(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
19 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.sub(
22 %orig = call i32 @llvm.amdgcn.buffer.atomic.sub(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
27 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.smin(
30 %orig = call i32 @llvm.amdgcn.buffer.atomic.smin(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
35 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.umin(
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Dllvm.amdgcn.image.atomic.ll1 ;RUN: opt -mtriple=amdgcn-mesa-mesa3d -analyze -divergence %s | FileCheck %s
3 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.image.atomic.swap.i32(
6 …%orig = call i32 @llvm.amdgcn.image.atomic.swap.i32(i32 %data, i32 %addr, <8 x i32> %rsrc, i1 0, i…
11 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.image.atomic.add.i32(
14 …%orig = call i32 @llvm.amdgcn.image.atomic.add.i32(i32 %data, i32 %addr, <8 x i32> %rsrc, i1 0, i1…
19 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.image.atomic.sub.i32(
22 …%orig = call i32 @llvm.amdgcn.image.atomic.sub.i32(i32 %data, i32 %addr, <8 x i32> %rsrc, i1 0, i1…
27 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.image.atomic.smin.i32(
30 …%orig = call i32 @llvm.amdgcn.image.atomic.smin.i32(i32 %data, i32 %addr, <8 x i32> %rsrc, i1 0, i…
35 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.image.atomic.umin.i32(
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