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Searched refs:ctx_cs (Results 1 – 3 of 3) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_pipeline.c3986 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_depth_stencil_state() argument
4041 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control); in radv_pipeline_generate_depth_stencil_state()
4042 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override); in radv_pipeline_generate_depth_stencil_state()
4043 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2); in radv_pipeline_generate_depth_stencil_state()
4047 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs, in radv_pipeline_generate_blend_state() argument
4051 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8); in radv_pipeline_generate_blend_state()
4052 radeon_emit_array(ctx_cs, blend->cb_blend_control, in radv_pipeline_generate_blend_state()
4054 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control); in radv_pipeline_generate_blend_state()
4055 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask); in radv_pipeline_generate_blend_state()
4059 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8); in radv_pipeline_generate_blend_state()
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Dradv_cmd_buffer.c1306 cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw || in radv_emit_graphics_pipeline()
1308 memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf, in radv_emit_graphics_pipeline()
1309 pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) { in radv_emit_graphics_pipeline()
1310 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw); in radv_emit_graphics_pipeline()
4193 assert(!pipeline->ctx_cs.cdw); in radv_emit_compute_pipeline()
Dradv_private.h1731 struct radeon_cmdbuf ctx_cs; member