| /external/llvm/test/MC/Mips/ |
| D | mips-fpu-instructions.s | 9 # CHECK: abs.d $f12, $f14 # encoding: [0x05,0x73,0x20,0x46]
11 # CHECK: add.d $f8, $f12, $f14 # encoding: [0x00,0x62,0x2e,0x46]
13 # CHECK: floor.w.d $f12, $f14 # encoding: [0x0f,0x73,0x20,0x46]
15 # CHECK: ceil.w.d $f12, $f14 # encoding: [0x0e,0x73,0x20,0x46]
17 # CHECK: mul.d $f8, $f12, $f14 # encoding: [0x02,0x62,0x2e,0x46]
19 # CHECK: neg.d $f12, $f14 # encoding: [0x07,0x73,0x20,0x46]
21 # CHECK: round.w.d $f12, $f14 # encoding: [0x0c,0x73,0x20,0x46]
23 # CHECK: sqrt.d $f12, $f14 # encoding: [0x04,0x73,0x20,0x46]
25 # CHECK: sub.d $f8, $f12, $f14 # encoding: [0x01,0x62,0x2e,0x46]
27 # CHECK: trunc.w.d $f12, $f14 # encoding: [0x0d,0x73,0x20,0x46]
[all …]
|
| /external/llvm-project/llvm/test/MC/Mips/ |
| D | mips-fpu-instructions.s | 9 # CHECK: abs.d $f12, $f14 # encoding: [0x05,0x73,0x20,0x46]
11 # CHECK: add.d $f8, $f12, $f14 # encoding: [0x00,0x62,0x2e,0x46]
13 # CHECK: floor.w.d $f12, $f14 # encoding: [0x0f,0x73,0x20,0x46]
15 # CHECK: ceil.w.d $f12, $f14 # encoding: [0x0e,0x73,0x20,0x46]
17 # CHECK: mul.d $f8, $f12, $f14 # encoding: [0x02,0x62,0x2e,0x46]
19 # CHECK: neg.d $f12, $f14 # encoding: [0x07,0x73,0x20,0x46]
21 # CHECK: round.w.d $f12, $f14 # encoding: [0x0c,0x73,0x20,0x46]
23 # CHECK: sqrt.d $f12, $f14 # encoding: [0x04,0x73,0x20,0x46]
25 # CHECK: sub.d $f8, $f12, $f14 # encoding: [0x01,0x62,0x2e,0x46]
27 # CHECK: trunc.w.d $f12, $f14 # encoding: [0x0d,0x73,0x20,0x46]
[all …]
|
| D | micromips-fpu-instructions.s | 128 # CHECK-EL: c.f.d $f12, $f14 # encoding: [0xcc,0x55,0x3c,0x04]
130 # CHECK-EL: c.un.d $f12, $f14 # encoding: [0xcc,0x55,0x7c,0x04]
132 # CHECK-EL: c.eq.d $f12, $f14 # encoding: [0xcc,0x55,0xbc,0x04]
134 # CHECK-EL: c.ueq.d $f12, $f14 # encoding: [0xcc,0x55,0xfc,0x04]
136 # CHECK-EL: c.olt.d $f12, $f14 # encoding: [0xcc,0x55,0x3c,0x05]
138 # CHECK-EL: c.ult.d $f12, $f14 # encoding: [0xcc,0x55,0x7c,0x05]
140 # CHECK-EL: c.ole.d $f12, $f14 # encoding: [0xcc,0x55,0xbc,0x05]
142 # CHECK-EL: c.ule.d $f12, $f14 # encoding: [0xcc,0x55,0xfc,0x05]
144 # CHECK-EL: c.sf.d $f12, $f14 # encoding: [0xcc,0x55,0x3c,0x06]
146 # CHECK-EL: c.ngle.d $f12, $f14 # encoding: [0xcc,0x55,0x7c,0x06]
[all …]
|
| /external/capstone/suite/MC/Mips/ |
| D | mips-fpu-instructions.s.cs | 2 0x05,0x73,0x20,0x46 = abs.d $f12, $f14
4 0x00,0x62,0x2e,0x46 = add.d $f8, $f12, $f14
6 0x0f,0x73,0x20,0x46 = floor.w.d $f12, $f14
8 0x0e,0x73,0x20,0x46 = ceil.w.d $f12, $f14
10 0x02,0x62,0x2e,0x46 = mul.d $f8, $f12, $f14
12 0x07,0x73,0x20,0x46 = neg.d $f12, $f14
14 0x0c,0x73,0x20,0x46 = round.w.d $f12, $f14
16 0x04,0x73,0x20,0x46 = sqrt.d $f12, $f14
18 0x01,0x62,0x2e,0x46 = sub.d $f8, $f12, $f14
20 0x0d,0x73,0x20,0x46 = trunc.w.d $f12, $f14
[all …]
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | select-flt.ll | 41 ; M3: mov.s $f13, $f14
58 ; CMOV-64: movn.s $f14, $f13, $[[T0]]
59 ; CMOV-64: mov.s $f0, $f14
62 ; SEL-64: sel.s $f0, $f14, $f13
81 ; M2: mov.s $f12, $f14
88 ; CMOV-32: movn.s $f14, $f12, $[[T0]]
89 ; CMOV-32: mov.s $f0, $f14
92 ; SEL-32: sel.s $f0, $f14, $f12
113 ; M2: c.olt.s $f12, $f14
117 ; M2: mov.s $f12, $f14
[all …]
|
| D | select-dbl.ll | 63 ; M3: mov.d $f13, $f14
69 ; CMOV-64: movn.d $f14, $f13, $[[T0]]
70 ; CMOV-64: mov.d $f0, $f14
73 ; SEL-64: sel.d $f0, $f14, $f13
94 ; M2: mov.d $f12, $f14
101 ; CMOV-32: movn.d $f14, $f12, $[[T1]]
102 ; CMOV-32: mov.d $f0, $f14
106 ; SEL-32: sel.d $f0, $f14, $f12
125 ; MM32R3: movn.d $f14, $f12, $[[T1]]
126 ; MM32R3: mov.d $f0, $f14
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | select-flt.ll | 76 ; M3-NEXT: mov.s $f0, $f14
83 ; CMOV64-NEXT: mov.s $f0, $f14
92 ; 64R6-NEXT: sel.s $f0, $f14, $f13
121 ; M2-NEXT: mov.s $f0, $f14
128 ; CMOV32R1-NEXT: mov.s $f0, $f14
135 ; CMOV32R2-NEXT: mov.s $f0, $f14
144 ; 32R6-NEXT: sel.s $f0, $f14, $f12
172 ; MM32R3: mov.s $f0, $f14 # <MCInst #{{.*}} FMOV_S
180 ; MM32R6-NEXT: sel.s $f0, $f14, $f12
191 ; M2-NEXT: c.olt.s $f12, $f14
[all …]
|
| D | select-dbl.ll | 82 ; M3-NEXT: mov.d $f0, $f14
89 ; CMOV64-NEXT: mov.d $f0, $f14
98 ; 64R6-NEXT: sel.d $f0, $f14, $f13
130 ; M2-NEXT: mov.d $f0, $f14
137 ; CMOV32R1-NEXT: mov.d $f0, $f14
145 ; CMOV32R2-NEXT: mov.d $f0, $f14
156 ; 32R6-NEXT: sel.d $f0, $f14, $f12
184 ; MM32R3: mov.d $f0, $f14 # <MCInst #{{.*}} FMOV_D32
194 ; MM32R6-NEXT: sel.d $f0, $f14, $f12
205 ; M2-NEXT: c.olt.d $f12, $f14
[all …]
|
| /external/llvm/test/CodeGen/Mips/ |
| D | fmadd1.ll | 26 ; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
32 ; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
37 ; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
42 ; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
46 ; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
51 ; 64R6-DAG: add.s $[[T1:f[0-9]+]], $[[T0]], $f14
66 ; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
72 ; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
77 ; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
82 ; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
[all …]
|
| D | fcmp.ll | 43 ; 32-C-DAG: c.eq.s $f12, $f14
50 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
60 ; MM32R3-DAG: c.eq.s $f12, $f14
63 ; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
77 ; 32-C-DAG: c.ule.s $f12, $f14
84 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
94 ; MM32R3-DAG: c.ule.s $f12, $f14
97 ; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
111 ; 32-C-DAG: c.ult.s $f12, $f14
118 ; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
[all …]
|
| D | select.ll | 149 ; 64: movn.s $f14, $f13, $4
150 ; 64: mov.s $f0, $f14
152 ; 64R2: movn.s $f14, $f13, $4
153 ; 64R2: mov.s $f0, $f14
157 ; 64R6: sel.s $[[CC]], $f14, $f13
185 ; 64: movn.d $f14, $f13, $4
186 ; 64: mov.d $f0, $f14
188 ; 64R2: movn.d $f14, $f13, $4
189 ; 64R2: mov.d $f0, $f14
193 ; 64R6: sel.d $[[CC]], $f14, $f13
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/Mips/ |
| D | fcmp.ll | 41 ; 32-C-DAG: c.eq.s $f12, $f14
48 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
58 ; MM32R3-DAG: c.eq.s $f12, $f14
61 ; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
74 ; 32-C-DAG: c.ule.s $f12, $f14
81 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
91 ; MM32R3-DAG: c.ule.s $f12, $f14
94 ; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
107 ; 32-C-DAG: c.ult.s $f12, $f14
114 ; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
[all …]
|
| D | fmadd1.ll | 37 ; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
43 ; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
48 ; 32R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
53 ; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
57 ; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
62 ; 64R6-NOMADD-DAG: add.s $[[T1:f[0-9]+]], $[[T0]], $f14
77 ; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
83 ; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
88 ; 32R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
93 ; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| D | float_arithmetic_operations.mir | 24 liveins: $f12, $f14
27 ; FP32: liveins: $f12, $f14
29 ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
34 ; FP64: liveins: $f12, $f14
36 ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
41 %1:fprb(s32) = COPY $f14
55 liveins: $f12, $f14
58 ; FP32: liveins: $f12, $f14
60 ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
65 ; FP64: liveins: $f12, $f14
[all …]
|
| D | fcmp.mir | 49 liveins: $f12, $f14
52 ; FP32: liveins: $f12, $f14
57 ; FP64: liveins: $f12, $f14
75 liveins: $f12, $f14
78 ; FP32: liveins: $f12, $f14
83 ; FP64: liveins: $f12, $f14
101 liveins: $f12, $f14
104 ; FP32: liveins: $f12, $f14
106 ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
113 ; FP64: liveins: $f12, $f14
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/ |
| D | float_arithmetic_operations.mir | 23 liveins: $f12, $f14
26 ; FP32: liveins: $f12, $f14
28 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
33 ; FP64: liveins: $f12, $f14
35 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
40 %1:_(s32) = COPY $f14
52 liveins: $f12, $f14
55 ; FP32: liveins: $f12, $f14
57 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY $f14
62 ; FP64: liveins: $f12, $f14
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/ |
| D | float_arithmetic_operations.mir | 24 liveins: $f12, $f14
27 ; FP32: liveins: $f12, $f14
29 ; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
34 ; FP64: liveins: $f12, $f14
36 ; FP64: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
41 %1:_(s32) = COPY $f14
54 liveins: $f12, $f14
57 ; FP32: liveins: $f12, $f14
59 ; FP32: [[COPY1:%[0-9]+]]:fprb(s32) = COPY $f14
64 ; FP64: liveins: $f12, $f14
[all …]
|
| /external/llvm/test/MC/Disassembler/Mips/mips32/ |
| D | valid-mips32-el.txt | 2 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
5 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
25 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
27 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
29 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
31 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
33 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
35 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
37 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
39 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]
|
| /external/llvm-project/llvm/test/MC/Disassembler/Mips/mips32/ |
| D | valid-mips32-el.txt | 2 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
5 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
25 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
27 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
29 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
31 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
33 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
35 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
37 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
39 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| D | valid-mips32r2-el.txt | 5 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
8 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
26 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
28 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
30 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
32 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
34 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
36 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
38 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
40 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| D | valid-mips32r3-el.txt | 2 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
5 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
23 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
25 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
27 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
29 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
31 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
33 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
35 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
37 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]
|
| /external/llvm-project/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| D | valid-mips32r5-el.txt | 3 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
6 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
25 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
27 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
29 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
31 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
33 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
35 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
37 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
39 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]
|
| /external/llvm-project/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| D | valid-mips32r3-el.txt | 3 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
6 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
25 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
27 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
29 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
31 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
33 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
35 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
37 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
39 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| D | valid-mips32r5-el.txt | 2 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
5 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
23 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
25 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
27 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
29 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
31 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
33 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
35 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
37 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]
|
| /external/llvm-project/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| D | valid-mips32r2-el.txt | 6 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
9 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
28 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
30 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
32 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
34 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
36 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
38 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
40 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
42 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]
|