| /external/llvm/test/CodeGen/AArch64/ |
| D | fp16-v16-instructions.ll | 38 ; CHECK-DAG: fcvtn2 [[S0]].4s, [[D1]]
39 ; CHECK-DAG: fcvtn2 [[S1]].4s, [[D3]]
40 ; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
41 ; CHECK-DAG: fcvtn2 [[S3]].4s, [[D7]]
89 ; CHECK-DAG: fcvtn2 [[S0]].4s, [[D1]]
90 ; CHECK-DAG: fcvtn2 [[S1]].4s, [[D3]]
91 ; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
92 ; CHECK-DAG: fcvtn2 [[S3]].4s, [[D7]]
|
| D | arm64-vcvt_f32_su32.ll | 65 ; CHECK: fcvtn2 v0.8h, v1.4s
|
| D | arm64-convert-v4f64.ll | 39 ; CHECK-DAG: fcvtn2 v[[MID]].4s, v[[RHS]].2d
|
| D | arm64-vcvt_f.ll | 34 ; CHECK: fcvtn2
|
| D | fp16-v4-instructions.ll | 171 ; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
214 ; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
|
| D | fp16-v8-instructions.ll | 303 ; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
355 ; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | fp16-v16-instructions.ll | 38 ; CHECK-DAG: fcvtn2 [[S0]].4s, [[D1]]
39 ; CHECK-DAG: fcvtn2 [[S1]].4s, [[D3]]
40 ; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
41 ; CHECK-DAG: fcvtn2 [[S3]].4s, [[D7]]
89 ; CHECK-DAG: fcvtn2 [[S0]].4s, [[D1]]
90 ; CHECK-DAG: fcvtn2 [[S1]].4s, [[D3]]
91 ; CHECK-DAG: fcvtn2 [[S2]].4s, [[D5]]
92 ; CHECK-DAG: fcvtn2 [[S3]].4s, [[D7]]
|
| D | arm64-vcvt_f.ll | 208 ; GENERIC-NEXT: fcvtn2 v0.4s, v1.2d
216 ; FAST-NEXT: fcvtn2 v0.4s, v1.2d
222 ; GISEL-NEXT: fcvtn2 v0.4s, v1.2d
|
| D | arm64-vcvt_f32_su32.ll | 65 ; CHECK: fcvtn2 v0.8h, v1.4s
|
| D | arm64-convert-v4f64.ll | 39 ; CHECK-DAG: fcvtn2 v[[MID]].4s, v[[RHS]].2d
|
| D | fp16-v4-instructions.ll | 195 ; CHECK-COMMON-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
242 ; CHECK-COMMON-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
|
| D | fp16-v8-instructions.ll | 328 ; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
381 ; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]]
|
| /external/capstone/suite/MC/AArch64/ |
| D | neon-simd-misc.s.cs | 134 0x82,0x68,0x21,0x4e = fcvtn2 v2.8h, v4.4s
135 0x06,0x69,0x61,0x4e = fcvtn2 v6.4s, v8.2d
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | neon-simd-misc.s | 423 fcvtn2 v2.8h, v4.4s
424 fcvtn2 v6.4s, v8.2d
|
| D | arm64-advsimd.s | 864 fcvtn2 v4.8h, v6.4s
865 fcvtn2 v5.4s, v7.2d
871 ; CHECK: fcvtn2 v4.8h, v6.4s ; encoding: [0xc4,0x68,0x21,0x4e]
872 ; CHECK: fcvtn2 v5.4s, v7.2d ; encoding: [0xe5,0x68,0x61,0x4e]
|
| D | neon-diagnostics.s | 5740 fcvtn2 v13.4h, v21.4s
5741 fcvtn2 v4.2s, v0.2d
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-misc.s | 423 fcvtn2 v2.8h, v4.4s
424 fcvtn2 v6.4s, v8.2d
|
| D | arm64-advsimd.s | 864 fcvtn2 v4.8h, v6.4s
865 fcvtn2 v5.4s, v7.2d
871 ; CHECK: fcvtn2 v4.8h, v6.4s ; encoding: [0xc4,0x68,0x21,0x4e]
872 ; CHECK: fcvtn2 v5.4s, v7.2d ; encoding: [0xe5,0x68,0x61,0x4e]
|
| D | neon-diagnostics.s | 5800 fcvtn2 v13.4h, v21.4s
5801 fcvtn2 v4.2s, v0.2d
|
| /external/llvm-project/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 560 # CHECK: fcvtn2 v0.8h, v0.4s
562 # CHECK: fcvtn2 v0.4s, v0.2d
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 560 # CHECK: fcvtn2 v0.8h, v0.4s
562 # CHECK: fcvtn2 v0.4s, v0.2d
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 2583 __ fcvtn2(v24.V4S(), v29.V2D()); in GenerateTestSequenceNEONFP() local
2584 __ fcvtn2(v4.V8H(), v10.V4S()); in GenerateTestSequenceNEONFP() local
|
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 4181 LogicVRegister fcvtn2(VectorFormat vform,
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 2229 0x~~~~~~~~~~~~~~~~ 4e616bb8 fcvtn2 v24.4s, v29.2d
2230 0x~~~~~~~~~~~~~~~~ 4e216944 fcvtn2 v4.8h, v10.4s
|
| D | log-disasm | 2229 0x~~~~~~~~~~~~~~~~ 4e616bb8 fcvtn2 v24.4s, v29.2d
2230 0x~~~~~~~~~~~~~~~~ 4e216944 fcvtn2 v4.8h, v10.4s
|