1; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK-CVT --check-prefix=CHECK 2; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK-FP16 --check-prefix=CHECK 3 4define <8 x half> @add_h(<8 x half> %a, <8 x half> %b) { 5entry: 6; CHECK-CVT-LABEL: add_h: 7; CHECK-CVT: fcvt 8; CHECK-CVT: fcvt 9; CHECK-CVT-DAG: fadd 10; CHECK-CVT-DAG: fcvt 11; CHECK-CVT-DAG: fcvt 12; CHECK-CVT-DAG: fadd 13; CHECK-CVT-DAG: fcvt 14; CHECK-CVT-DAG: fcvt 15; CHECK-CVT-DAG: fadd 16; CHECK-CVT-DAG: fcvt 17; CHECK-CVT-DAG: fcvt 18; CHECK-CVT-DAG: fadd 19; CHECK-CVT-DAG: fcvt 20; CHECK-CVT-DAG: fcvt 21; CHECK-CVT-DAG: fadd 22; CHECK-CVT-DAG: fcvt 23; CHECK-CVT-DAG: fcvt 24; CHECK-CVT-DAG: fadd 25; CHECK-CVT-DAG: fcvt 26; CHECK-CVT-DAG: fcvt 27; CHECK-CVT-DAG: fadd 28; CHECK-CVT-DAG: fcvt 29; CHECK-CVT-DAG: fcvt 30; CHECK-CVT-DAG: fadd 31; CHECK-CVT-DAG: fcvt 32; CHECK-CVT-DAG: fcvt 33; CHECK-CVT-DAG: fcvt 34; CHECK-CVT-DAG: fcvt 35; CHECK-CVT-DAG: fcvt 36; CHECK-CVT-DAG: fcvt 37; CHECK-CVT-DAG: fcvt 38; CHECK-CVT: fcvt 39 40; CHECK-FP16-LABEL: add_h: 41; CHECK-FP16: fadd v0.8h, v0.8h, v1.8h 42; CHECK-FP16-NEXT: ret 43 44 %0 = fadd <8 x half> %a, %b 45 ret <8 x half> %0 46} 47 48 49define <8 x half> @sub_h(<8 x half> %a, <8 x half> %b) { 50entry: 51; CHECK-CVT-LABEL: sub_h: 52; CHECK-CVT: fcvt 53; CHECK-CVT: fcvt 54; CHECK-CVT-DAG: fsub 55; CHECK-CVT-DAG: fcvt 56; CHECK-CVT-DAG: fcvt 57; CHECK-CVT-DAG: fsub 58; CHECK-CVT-DAG: fcvt 59; CHECK-CVT-DAG: fcvt 60; CHECK-CVT-DAG: fsub 61; CHECK-CVT-DAG: fcvt 62; CHECK-CVT-DAG: fcvt 63; CHECK-CVT-DAG: fsub 64; CHECK-CVT-DAG: fcvt 65; CHECK-CVT-DAG: fcvt 66; CHECK-CVT-DAG: fsub 67; CHECK-CVT-DAG: fcvt 68; CHECK-CVT-DAG: fcvt 69; CHECK-CVT-DAG: fsub 70; CHECK-CVT-DAG: fcvt 71; CHECK-CVT-DAG: fcvt 72; CHECK-CVT-DAG: fsub 73; CHECK-CVT-DAG: fcvt 74; CHECK-CVT-DAG: fcvt 75; CHECK-CVT-DAG: fsub 76; CHECK-CVT-DAG: fcvt 77; CHECK-CVT-DAG: fcvt 78; CHECK-CVT-DAG: fcvt 79; CHECK-CVT-DAG: fcvt 80; CHECK-CVT-DAG: fcvt 81; CHECK-CVT-DAG: fcvt 82; CHECK-CVT-DAG: fcvt 83; CHECK-CVT: fcvt 84 85; CHECK-FP16-LABEL: sub_h: 86; CHECK-FP16: fsub v0.8h, v0.8h, v1.8h 87; CHECK-FP16-NEXT: ret 88 89 %0 = fsub <8 x half> %a, %b 90 ret <8 x half> %0 91} 92 93 94define <8 x half> @mul_h(<8 x half> %a, <8 x half> %b) { 95entry: 96; CHECK-CVT-LABEL: mul_h: 97; CHECK-CVT: fcvt 98; CHECK-CVT: fcvt 99; CHECK-CVT-DAG: fmul 100; CHECK-CVT-DAG: fcvt 101; CHECK-CVT-DAG: fcvt 102; CHECK-CVT-DAG: fmul 103; CHECK-CVT-DAG: fcvt 104; CHECK-CVT-DAG: fcvt 105; CHECK-CVT-DAG: fmul 106; CHECK-CVT-DAG: fcvt 107; CHECK-CVT-DAG: fcvt 108; CHECK-CVT-DAG: fmul 109; CHECK-CVT-DAG: fcvt 110; CHECK-CVT-DAG: fcvt 111; CHECK-CVT-DAG: fmul 112; CHECK-CVT-DAG: fcvt 113; CHECK-CVT-DAG: fcvt 114; CHECK-CVT-DAG: fmul 115; CHECK-CVT-DAG: fcvt 116; CHECK-CVT-DAG: fcvt 117; CHECK-CVT-DAG: fmul 118; CHECK-CVT-DAG: fcvt 119; CHECK-CVT-DAG: fcvt 120; CHECK-CVT-DAG: fmul 121; CHECK-CVT-DAG: fcvt 122; CHECK-CVT-DAG: fcvt 123; CHECK-CVT-DAG: fcvt 124; CHECK-CVT-DAG: fcvt 125; CHECK-CVT-DAG: fcvt 126; CHECK-CVT-DAG: fcvt 127; CHECK-CVT-DAG: fcvt 128; CHECK-CVT: fcvt 129 130; CHECK-FP16-LABEL: mul_h: 131; CHECK-FP16: fmul v0.8h, v0.8h, v1.8h 132; CHECK-FP16-NEXT: ret 133 134 %0 = fmul <8 x half> %a, %b 135 ret <8 x half> %0 136} 137 138 139define <8 x half> @div_h(<8 x half> %a, <8 x half> %b) { 140entry: 141; CHECK-CVT-LABEL: div_h: 142; CHECK-CVT: fcvt 143; CHECK-CVT: fcvt 144; CHECK-CVT-DAG: fdiv 145; CHECK-CVT-DAG: fcvt 146; CHECK-CVT-DAG: fcvt 147; CHECK-CVT-DAG: fdiv 148; CHECK-CVT-DAG: fcvt 149; CHECK-CVT-DAG: fcvt 150; CHECK-CVT-DAG: fdiv 151; CHECK-CVT-DAG: fcvt 152; CHECK-CVT-DAG: fcvt 153; CHECK-CVT-DAG: fdiv 154; CHECK-CVT-DAG: fcvt 155; CHECK-CVT-DAG: fcvt 156; CHECK-CVT-DAG: fdiv 157; CHECK-CVT-DAG: fcvt 158; CHECK-CVT-DAG: fcvt 159; CHECK-CVT-DAG: fdiv 160; CHECK-CVT-DAG: fcvt 161; CHECK-CVT-DAG: fcvt 162; CHECK-CVT-DAG: fdiv 163; CHECK-CVT-DAG: fcvt 164; CHECK-CVT-DAG: fcvt 165; CHECK-CVT-DAG: fdiv 166; CHECK-CVT-DAG: fcvt 167; CHECK-CVT-DAG: fcvt 168; CHECK-CVT-DAG: fcvt 169; CHECK-CVT-DAG: fcvt 170; CHECK-CVT-DAG: fcvt 171; CHECK-CVT-DAG: fcvt 172; CHECK-CVT-DAG: fcvt 173; CHECK-CVT: fcvt 174 175; CHECK-FP16-LABEL: div_h: 176; CHECK-FP16: fdiv v0.8h, v0.8h, v1.8h 177; CHECK-FP16-NEXT: ret 178 179 %0 = fdiv <8 x half> %a, %b 180 ret <8 x half> %0 181} 182 183 184define <8 x half> @load_h(<8 x half>* %a) { 185entry: 186; CHECK-LABEL: load_h: 187; CHECK: ldr q0, [x0] 188 %0 = load <8 x half>, <8 x half>* %a, align 4 189 ret <8 x half> %0 190} 191 192 193define void @store_h(<8 x half>* %a, <8 x half> %b) { 194entry: 195; CHECK-LABEL: store_h: 196; CHECK: str q0, [x0] 197 store <8 x half> %b, <8 x half>* %a, align 4 198 ret void 199} 200 201define <8 x half> @s_to_h(<8 x float> %a) { 202; CHECK-LABEL: s_to_h: 203; CHECK-DAG: fcvtn v0.4h, v0.4s 204; CHECK-DAG: fcvtn [[REG:v[0-9+]]].4h, v1.4s 205; CHECK: mov v0.d[1], [[REG]].d[0] 206 %1 = fptrunc <8 x float> %a to <8 x half> 207 ret <8 x half> %1 208} 209 210define <8 x half> @d_to_h(<8 x double> %a) { 211; CHECK-LABEL: d_to_h: 212; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1] 213; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1] 214; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1] 215; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1] 216; CHECK-DAG: fcvt h 217; CHECK-DAG: fcvt h 218; CHECK-DAG: fcvt h 219; CHECK-DAG: fcvt h 220; CHECK-DAG: fcvt h 221; CHECK-DAG: fcvt h 222; CHECK-DAG: fcvt h 223; CHECK-DAG: fcvt h 224; CHECK-DAG: mov v{{[0-9]+}}.h 225; CHECK-DAG: mov v{{[0-9]+}}.h 226; CHECK-DAG: mov v{{[0-9]+}}.h 227; CHECK-DAG: mov v{{[0-9]+}}.h 228; CHECK-DAG: mov v{{[0-9]+}}.h 229; CHECK-DAG: mov v{{[0-9]+}}.h 230; CHECK-DAG: mov v{{[0-9]+}}.h 231; CHECK-DAG: mov v{{[0-9]+}}.h 232 %1 = fptrunc <8 x double> %a to <8 x half> 233 ret <8 x half> %1 234} 235 236define <8 x float> @h_to_s(<8 x half> %a) { 237; CHECK-LABEL: h_to_s: 238; CHECK: fcvtl2 v1.4s, v0.8h 239; CHECK: fcvtl v0.4s, v0.4h 240 %1 = fpext <8 x half> %a to <8 x float> 241 ret <8 x float> %1 242} 243 244define <8 x double> @h_to_d(<8 x half> %a) { 245; CHECK-LABEL: h_to_d: 246; CHECK-DAG: mov h{{[0-9]+}}, v0.h 247; CHECK-DAG: mov h{{[0-9]+}}, v0.h 248; CHECK-DAG: mov h{{[0-9]+}}, v0.h 249; CHECK-DAG: mov h{{[0-9]+}}, v0.h 250; CHECK-DAG: mov h{{[0-9]+}}, v0.h 251; CHECK-DAG: mov h{{[0-9]+}}, v0.h 252; CHECK-DAG: mov h{{[0-9]+}}, v0.h 253; CHECK-DAG: fcvt d 254; CHECK-DAG: fcvt d 255; CHECK-DAG: fcvt d 256; CHECK-DAG: fcvt d 257; CHECK-DAG: fcvt d 258; CHECK-DAG: fcvt d 259; CHECK-DAG: fcvt d 260; CHECK-DAG: fcvt d 261 %1 = fpext <8 x half> %a to <8 x double> 262 ret <8 x double> %1 263} 264 265 266define <8 x half> @bitcast_i_to_h(float, <8 x i16> %a) { 267; CHECK-LABEL: bitcast_i_to_h: 268; CHECK: mov v0.16b, v1.16b 269 %2 = bitcast <8 x i16> %a to <8 x half> 270 ret <8 x half> %2 271} 272 273define <8 x i16> @bitcast_h_to_i(float, <8 x half> %a) { 274; CHECK-LABEL: bitcast_h_to_i: 275; CHECK: mov v0.16b, v1.16b 276 %2 = bitcast <8 x half> %a to <8 x i16> 277 ret <8 x i16> %2 278} 279 280 281define <8 x half> @sitofp_i8(<8 x i8> %a) #0 { 282; CHECK-LABEL: sitofp_i8: 283; CHECK-NEXT: sshll v[[REG1:[0-9]+]].8h, v0.8b, #0 284; CHECK-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0 285; CHECK-NEXT: sshll [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0 286; CHECK-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]] 287; CHECK-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]] 288; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]] 289; CHECK-DAG: fcvtn v0.4h, [[HIF]] 290; CHECK: mov v0.d[1], v[[LOREG]].d[0] 291 %1 = sitofp <8 x i8> %a to <8 x half> 292 ret <8 x half> %1 293} 294 295 296define <8 x half> @sitofp_i16(<8 x i16> %a) #0 { 297; CHECK-LABEL: sitofp_i16: 298; CHECK-FP16-NEXT: scvtf v0.8h, v0.8h 299; CHECK-CVT-NEXT: sshll2 [[LO:v[0-9]+\.4s]], v0.8h, #0 300; CHECK-CVT-NEXT: sshll [[HI:v[0-9]+\.4s]], v0.4h, #0 301; CHECK-CVT-DAG: scvtf [[HIF:v[0-9]+\.4s]], [[HI]] 302; CHECK-CVT-DAG: scvtf [[LOF:v[0-9]+\.4s]], [[LO]] 303; CHECK-CVT-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]] 304; CHECK-CVT-DAG: fcvtn v0.4h, [[HIF]] 305; CHECK-CVT-NEXT: mov v0.d[1], v[[LOREG]].d[0] 306 %1 = sitofp <8 x i16> %a to <8 x half> 307 ret <8 x half> %1 308} 309 310 311define <8 x half> @sitofp_i32(<8 x i32> %a) #0 { 312; CHECK-LABEL: sitofp_i32: 313; CHECK-DAG: scvtf [[OP1:v[0-9]+\.4s]], v0.4s 314; CHECK-DAG: scvtf [[OP2:v[0-9]+\.4s]], v1.4s 315; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]] 316; CHECK-DAG: fcvtn v0.4h, [[OP1]] 317; CHECK: mov v0.d[1], v[[REG]].d[0] 318 %1 = sitofp <8 x i32> %a to <8 x half> 319 ret <8 x half> %1 320} 321 322 323define <8 x half> @sitofp_i64(<8 x i64> %a) #0 { 324; CHECK-LABEL: sitofp_i64: 325; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d 326; CHECK-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d 327; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]] 328; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]] 329; CHECK: fcvtn v0.4h, [[OP3]].4s 330 %1 = sitofp <8 x i64> %a to <8 x half> 331 ret <8 x half> %1 332} 333 334define <8 x half> @uitofp_i8(<8 x i8> %a) #0 { 335; CHECK-LABEL: uitofp_i8: 336; CHECK-NEXT: ushll v[[REG1:[0-9]+]].8h, v0.8b, #0 337; CHECK-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v[[REG1]].8h, #0 338; CHECK-NEXT: ushll [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0 339; CHECK-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]] 340; CHECK-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]] 341; CHECK-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]] 342; CHECK-DAG: fcvtn v0.4h, [[HIF]] 343; CHECK: mov v0.d[1], v[[LOREG]].d[0] 344 %1 = uitofp <8 x i8> %a to <8 x half> 345 ret <8 x half> %1 346} 347 348 349define <8 x half> @uitofp_i16(<8 x i16> %a) #0 { 350; CHECK-LABEL: uitofp_i16: 351; CHECK-FP16-NEXT: ucvtf v0.8h, v0.8h 352; CHECK-CVT-NEXT: ushll2 [[LO:v[0-9]+\.4s]], v0.8h, #0 353; CHECK-CVT-NEXT: ushll [[HI:v[0-9]+\.4s]], v0.4h, #0 354; CHECK-CVT-DAG: ucvtf [[HIF:v[0-9]+\.4s]], [[HI]] 355; CHECK-CVT-DAG: ucvtf [[LOF:v[0-9]+\.4s]], [[LO]] 356; CHECK-CVT-DAG: fcvtn v[[LOREG:[0-9]+]].4h, [[LOF]] 357; CHECK-CVT-DAG: fcvtn v0.4h, [[HIF]] 358; CHECK-CVT-NEXT: mov v0.d[1], v[[LOREG]].d[0] 359 %1 = uitofp <8 x i16> %a to <8 x half> 360 ret <8 x half> %1 361} 362 363 364define <8 x half> @uitofp_i32(<8 x i32> %a) #0 { 365; CHECK-LABEL: uitofp_i32: 366; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s 367; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.4s]], v1.4s 368; CHECK-DAG: fcvtn v[[REG:[0-9]+]].4h, [[OP2]] 369; CHECK-DAG: fcvtn v0.4h, [[OP1]] 370; CHECK: mov v0.d[1], v[[REG]].d[0] 371 %1 = uitofp <8 x i32> %a to <8 x half> 372 ret <8 x half> %1 373} 374 375 376define <8 x half> @uitofp_i64(<8 x i64> %a) #0 { 377; CHECK-LABEL: uitofp_i64: 378; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d 379; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d 380; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]] 381; CHECK-DAG: fcvtn2 [[OP3]].4s, [[OP2]] 382; CHECK: fcvtn v0.4h, [[OP3]].4s 383 %1 = uitofp <8 x i64> %a to <8 x half> 384 ret <8 x half> %1 385} 386 387define void @test_insert_at_zero(half %a, <8 x half>* %b) #0 { 388; CHECK-LABEL: test_insert_at_zero: 389; CHECK-NEXT: str q0, [x0] 390; CHECK-NEXT: ret 391 %1 = insertelement <8 x half> undef, half %a, i64 0 392 store <8 x half> %1, <8 x half>* %b, align 4 393 ret void 394} 395 396define <8 x i8> @fptosi_i8(<8 x half> %a) #0 { 397; CHECK-LABEL: fptosi_i8: 398; CHECK-FP16-NEXT: fcvtzs [[LO:v[0-9]+\.8h]], v0.8h 399; CHECK-CVT-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h 400; CHECK-CVT-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h 401; CHECK-CVT-DAG: fcvtzs [[LOF32:v[0-9]+\.4s]], [[LO]] 402; CHECK-CVT-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]] 403; CHECK-CVT-DAG: fcvtzs [[HIF32:v[0-9]+\.4s]], [[HI]] 404; CHECK-CVT-DAG: xtn2 [[I16]].8h, [[HIF32]] 405; CHECK-CVT-DAG: xtn v0.8b, [[I16]].8h 406; CHECK-FP16-NEXT: xtn v0.8b, [[LO]] 407; CHECK-NEXT: ret 408 %1 = fptosi<8 x half> %a to <8 x i8> 409 ret <8 x i8> %1 410} 411 412define <8 x i16> @fptosi_i16(<8 x half> %a) #0 { 413; CHECK-LABEL: fptosi_i16: 414; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h 415; CHECK-CVT_DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h 416; CHECK-CVT_DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h 417; CHECK-CVT_DAG: fcvtzs [[LOF32:v[0-9]+\.4s]], [[LO]] 418; CHECK-CVT_DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]] 419; CHECK-CVT_DAG: fcvtzs [[HIF32:v[0-9]+\.4s]], [[HI]] 420; CHECK-CVT_DAG: xtn2 [[I16]].8h, [[HIF32]] 421; CHECK-COMMON_NEXT: ret 422 %1 = fptosi<8 x half> %a to <8 x i16> 423 ret <8 x i16> %1 424} 425 426define <8 x i8> @fptoui_i8(<8 x half> %a) #0 { 427; CHECK-LABEL: fptoui_i8: 428; CHECK-FP16-NEXT: fcvtzu [[LO:v[0-9]+\.8h]], v0.8h 429; CHECK-CVT-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h 430; CHECK-CVT-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h 431; CHECK-CVT-DAG: fcvtzu [[LOF32:v[0-9]+\.4s]], [[LO]] 432; CHECK-CVT-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]] 433; CHECK-CVT-DAG: fcvtzu [[HIF32:v[0-9]+\.4s]], [[HI]] 434; CHECK-CVT-DAG: xtn2 [[I16]].8h, [[HIF32]] 435; CHECK-CVT-DAG: xtn v0.8b, [[I16]].8h 436; CHECK-FP16-NEXT: xtn v0.8b, [[LO]] 437; CHECK-NEXT: ret 438 %1 = fptoui<8 x half> %a to <8 x i8> 439 ret <8 x i8> %1 440} 441 442define <8 x i16> @fptoui_i16(<8 x half> %a) #0 { 443; CHECK-LABEL: fptoui_i16: 444; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h 445; CHECK-CVT-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h 446; CHECK-CVT-DAG: fcvtl2 [[HI:v[0-9]+\.4s]], v0.8h 447; CHECK-CVT-DAG: fcvtzu [[LOF32:v[0-9]+\.4s]], [[LO]] 448; CHECK-CVT-DAG: xtn [[I16:v[0-9]+]].4h, [[LOF32]] 449; CHECK-CVT-DAG: fcvtzu [[HIF32:v[0-9]+\.4s]], [[HI]] 450; CHECK-CVT-DAG: xtn2 [[I16]].8h, [[HIF32]] 451; CHECK-NEXT: ret 452 %1 = fptoui<8 x half> %a to <8 x i16> 453 ret <8 x i16> %1 454} 455 456define <8 x i1> @test_fcmp_une(<8 x half> %a, <8 x half> %b) #0 { 457; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 458 459; CHECK-FP16-LABEL: test_fcmp_une: 460; CHECK-FP16-NOT: fcvt 461; CHECK-FP16-DAG: fcmeq v{{[0-9]}}.8h, v{{[0-9]}}.8h 462 463 %1 = fcmp une <8 x half> %a, %b 464 ret <8 x i1> %1 465} 466 467define <8 x i1> @test_fcmp_ueq(<8 x half> %a, <8 x half> %b) #0 { 468; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 469 470; CHECK-FP16-LABEL: test_fcmp_ueq: 471; CHECK-FP16-NOT: fcvt 472; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h 473; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h 474 475 %1 = fcmp ueq <8 x half> %a, %b 476 ret <8 x i1> %1 477} 478 479define <8 x i1> @test_fcmp_ugt(<8 x half> %a, <8 x half> %b) #0 { 480; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 481 482; CHECK-FP16-LABEL: test_fcmp_ugt: 483; CHECK-FP16-NOT: fcvt 484; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h 485 486 %1 = fcmp ugt <8 x half> %a, %b 487 ret <8 x i1> %1 488} 489 490define <8 x i1> @test_fcmp_uge(<8 x half> %a, <8 x half> %b) #0 { 491; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 492 493; CHECK-FP16-LABEL: test_fcmp_uge: 494; CHECK-FP16-NOT: fcvt 495; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h 496 497 %1 = fcmp uge <8 x half> %a, %b 498 ret <8 x i1> %1 499} 500 501define <8 x i1> @test_fcmp_ult(<8 x half> %a, <8 x half> %b) #0 { 502; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 503 504; CHECK-FP16-LABEL: test_fcmp_ult: 505; CHECK-FP16-NOT: fcvt 506; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h 507 508 %1 = fcmp ult <8 x half> %a, %b 509 ret <8 x i1> %1 510} 511 512define <8 x i1> @test_fcmp_ule(<8 x half> %a, <8 x half> %b) #0 { 513; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 514 515; CHECK-FP16-LABEL: test_fcmp_ule: 516; CHECK-FP16-NOT: fcvt 517; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h 518 519 %1 = fcmp ule <8 x half> %a, %b 520 ret <8 x i1> %1 521} 522 523define <8 x i1> @test_fcmp_uno(<8 x half> %a, <8 x half> %b) #0 { 524; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 525 526; CHECK-FP16-LABEL: test_fcmp_uno: 527; CHECK-FP16-NOT: fcvt 528; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h 529; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h 530 531 %1 = fcmp uno <8 x half> %a, %b 532 ret <8 x i1> %1 533} 534 535define <8 x i1> @test_fcmp_one(<8 x half> %a, <8 x half> %b) #0 { 536; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 537 538; CHECK-FP16-LABEL: test_fcmp_one: 539; CHECK-FP16-NOT: fcvt 540; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h 541; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h 542 543 %1 = fcmp one <8 x half> %a, %b 544 ret <8 x i1> %1 545} 546 547define <8 x i1> @test_fcmp_oeq(<8 x half> %a, <8 x half> %b) #0 { 548; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 549 550; CHECK-FP16-LABEL: test_fcmp_oeq: 551; CHECK-FP16-NOT: fcvt 552; CHECK-FP16-DAG: fcmeq v{{[0-9]}}.8h, v{{[0-9]}}.8h 553 554 %1 = fcmp oeq <8 x half> %a, %b 555 ret <8 x i1> %1 556} 557 558define <8 x i1> @test_fcmp_ogt(<8 x half> %a, <8 x half> %b) #0 { 559; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 560 561; CHECK-FP16-LABEL: test_fcmp_ogt: 562; CHECK-FP16-NOT: fcvt 563; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h 564 565 %1 = fcmp ogt <8 x half> %a, %b 566 ret <8 x i1> %1 567} 568 569define <8 x i1> @test_fcmp_oge(<8 x half> %a, <8 x half> %b) #0 { 570; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 571 572; CHECK-FP16-LABEL: test_fcmp_oge: 573; CHECK-FP16-NOT: fcvt 574; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h 575 576 %1 = fcmp oge <8 x half> %a, %b 577 ret <8 x i1> %1 578} 579 580define <8 x i1> @test_fcmp_olt(<8 x half> %a, <8 x half> %b) #0 { 581; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 582 583; CHECK-FP16-LABEL: test_fcmp_olt: 584; CHECK-FP16-NOT: fcvt 585; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h 586 587 %1 = fcmp olt <8 x half> %a, %b 588 ret <8 x i1> %1 589} 590 591define <8 x i1> @test_fcmp_ole(<8 x half> %a, <8 x half> %b) #0 { 592; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 593 594; CHECK-FP16-LABEL: test_fcmp_ole: 595; CHECK-FP16-NOT: fcvt 596; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h 597 598 %1 = fcmp ole <8 x half> %a, %b 599 ret <8 x i1> %1 600} 601 602define <8 x i1> @test_fcmp_ord(<8 x half> %a, <8 x half> %b) #0 { 603; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests, so skipped for -fullfp16. 604 605; CHECK-FP16-LABEL: test_fcmp_ord: 606; CHECK-FP16-NOT: fcvt 607; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h 608; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h 609 610 %1 = fcmp ord <8 x half> %a, %b 611 ret <8 x i1> %1 612} 613 614attributes #0 = { nounwind } 615