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Searched refs:flh (Results 1 – 13 of 13) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/RISCV/
Dhalf-mem.ll7 define half @flh(half *%a) nounwind {
8 ; RV32IZFH-LABEL: flh:
10 ; RV32IZFH-NEXT: flh ft0, 0(a0)
11 ; RV32IZFH-NEXT: flh ft1, 6(a0)
15 ; RV64IZFH-LABEL: flh:
17 ; RV64IZFH-NEXT: flh ft0, 0(a0)
18 ; RV64IZFH-NEXT: flh ft1, 6(a0)
24 ; Use both loaded values in an FP op to ensure an flh is used, even for the
63 ; RV32IZFH-NEXT: flh ft0, %lo(G)(a0)
66 ; RV32IZFH-NEXT: flh ft0, 18(a0)
[all …]
Dhalf-imm.ll12 ; RV32IZFH-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
18 ; RV64IZFH-NEXT: flh fa0, %lo(.LCPI0_0)(a0)
27 ; RV32IZFH-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
34 ; RV64IZFH-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
Dzfh-imm.ll38 ; RV32IZFH-NEXT: flh fa0, %lo(.LCPI1_0)(a0)
44 ; RV32IDZFH-NEXT: flh fa0, %lo(.LCPI1_0)(a0)
50 ; RV64IZFH-NEXT: flh fa0, %lo(.LCPI1_0)(a0)
56 ; RV64IDZFH-NEXT: flh fa0, %lo(.LCPI1_0)(a0)
/external/llvm-project/llvm/test/MC/RISCV/
Drv32zfh-valid.s12 # CHECK-ASM-AND-OBJ: flh ft0, 12(a0)
14 flh f0, 12(a0) label
15 # CHECK-ASM-AND-OBJ: flh ft1, 4(ra)
17 flh f1, +4(ra) label
18 # CHECK-ASM-AND-OBJ: flh ft2, -2048(a3)
20 flh f2, -2048(x13) label
21 # CHECK-ASM-AND-OBJ: flh ft3, -2048(s1)
23 flh f3, %lo(2048)(s1) label
24 # CHECK-ASM-AND-OBJ: flh ft4, 2047(s2)
26 flh f4, 2047(s2) label
[all …]
Drv32zfh-invalid.s6 flh ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo/%tpre… label
10 flh ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction label
14 flh ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction label
15 flh ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register label
Drvzfh-pseudos.s6 # CHECK: flh fa2, %pcrel_lo(.Lpcrel_hi0)(a2)
7 flh fa2, a_symbol, a2 label
Drvzfh-aliases-valid.s50 # CHECK-INST: flh ft0, 0(a0)
51 # CHECK-ALIAS: flh ft0, 0(a0)
52 flh f0, (x10) label
/external/python/cpython3/Lib/idlelib/idle_test/
Dtest_outwin.py149 flh = outwin.file_line_helper
160 self.assertEqual(flh(line), expected_output)
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoZfh.td73 "flh", "$rd, ${imm12}(${rs1})">,
228 def : InstAlias<"flh $rd, (${rs1})", (FLH FPR16:$rd, GPR:$rs1, 0), 0>;
242 def PseudoFLH : PseudoFloatLoad<"flh", FPR16>;
/external/icu/icu4c/source/data/misc/
DsupplementalData.txt5499 "flh~i",
/external/cldr/tools/java/org/unicode/cldr/util/data/
Diso-639-3_Name_Index.tab2008 flh Foau Foau
Diso-639-3.tab1922 flh I L Foau
Dlanguage-subtag-registry11315 Subtag: flh